VHDL-FPGA-Verilog List Page 3281

VHDL-FPGA-Verilog list

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mms Downloaded：0: (1) The three-digit electronic code lock, through the input of the digital control lock switch (2) unlock their own during the user to set a password (3), enter the unlock password is correct
Update : 2025-04-04 Size : 179kb Publisher :
qdq Downloaded：0: (1) is used to contest a powerful four Responder (2) to answer in 20 seconds after the start of countdown, countdown display time-out after no one to answer in (3) can show to answer in station ID (4), enter the answer i
Update : 2025-04-04 Size : 686kb Publisher :
ask Downloaded：0: Designed to ask a modulator and demodulator, the input clock clk, enter a start signal start, enter the baseband data signal din and the output modulated signal ask
Update : 2025-04-04 Size : 133kb Publisher :
au Downloaded：0: UART controller based on AMBA APB
Update : 2025-04-04 Size : 7kb Publisher : Samuel Xu
hdlc Downloaded：0: design of HDLC
Update : 2025-04-04 Size : 3.53mb Publisher : hanjinchao
JmsQuartzTest Downloaded：0: JmsQuartzTest JmsQuartzTest JmsQuartzTest
Update : 2025-04-04 Size : 9.29mb Publisher : thismonth
8bitRISCCPU Downloaded：0: 8bit RISC cpu design
Update : 2025-04-04 Size : 797kb Publisher : dyfdown
UARTE Downloaded：0: A UART module writen in VHDL.
Update : 2025-04-04 Size : 475kb Publisher : 安宁
82_Examples_for_VHDL_and_Verilog_code Downloaded：0: 82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.
Update : 2025-04-04 Size : 79kb Publisher : M
Verilog Downloaded：0: basic verilog for students
Update : 2025-04-04 Size : 7.84mb Publisher : zq
20096411m5349886 Downloaded：0: This procedure generated to achieve an arbitrary duty cycle
Update : 2025-04-04 Size : 1kb Publisher : linjinwen
VHDL Downloaded：0: vhdl
Update : 2025-04-04 Size : 250kb Publisher : david

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