VHDL-FPGA-Verilog List Page 3692

VHDL-FPGA-Verilog list

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rs_enc Downloaded：0: Verilog code for RS-(255,239) encoder.
Update : 2025-01-27 Size : 3kb Publisher : sharat
z Downloaded：0: Description Sramoc (K, M) said the figures used in 0,1,2 ..., K-1 component of the natural number M be the smallest number divisible. Given K, M, for Sramoc (K, M). For example, K = 2, M = 7, when, Sramoc (2, 7) = 1001.
Update : 2025-01-27 Size : 2kb Publisher : z
xapp923 Downloaded：0: xapp from xilinx very hard to find and very usefull application note from the great firm from USA
Update : 2025-01-27 Size : 131kb Publisher : ARS
LCD Downloaded：0: LCD1602-driven FPGA-based, verilog code debugging has been successful
Update : 2025-01-27 Size : 1.05mb Publisher : liang ming
newdds Downloaded：0: FPGA-based algorithm cordic, has passed the back-end FPGA simulation
Update : 2025-01-27 Size : 1.88mb Publisher : liang ming
Coder Downloaded：0: This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence
Update : 2025-01-27 Size : 1kb Publisher : 石云
Decoder Downloaded：0: This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences
Update : 2025-01-27 Size : 1kb Publisher : 石云
HDB3Decoder Downloaded：0: This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences
Update : 2025-01-27 Size : 1kb Publisher : 石云
adder Downloaded：0: verilog for full_adder
Update : 2025-01-27 Size : 1kb Publisher : max
simple_verilog Downloaded：0: cycloneII Quartus verilog to develop a simple sequential circuit
Update : 2025-01-27 Size : 257kb Publisher : ray
DDS Downloaded：0: DDS achieved Quartus using IP core provided by altera
Update : 2025-01-27 Size : 82kb Publisher : ray
golomb Downloaded：0: golomb coding for lossless image compression, based on the platform quartusii.
Update : 2025-01-27 Size : 148kb Publisher : Tangyao

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