VHDL-FPGA-Verilog List Page 375

VHDL-FPGA-Verilog list

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SEG7_IF Downloaded：0: SEG7_IP.v is the seven segment digital tube driver, in line with the Avalon bus protocol, you can directly add the seven segment digital tube IP nuclear use.
Update : 2025-01-17 Size : 1kb Publisher : ww
2016 Downloaded：0: VHDL some projects can be used as a reference, water lights, serial port FIR, keypad, digital control and so on
Update : 2025-01-17 Size : 5.75mb Publisher : 张任
new_project Downloaded：0: This design is a vending machine control system design based on FPGA. The design uses FPGA as a master, vending machine control system design. Analog vending machine cargo information storage, selection and purchase of g
Update : 2025-01-17 Size : 3.88mb Publisher : 张任
usart_txd_mk3 Downloaded：0: Using Verilog write serial transmission program, we hope to be of some use
Update : 2025-01-17 Size : 3.06mb Publisher : 缪家骏
Vending-Machine-using-Moore Downloaded：0: Vending Machine simulation using Moore sequence
Update : 2025-01-17 Size : 45kb Publisher : Japerski
Mealy Downloaded：0: Example of Mealy sequence in VHDL
Update : 2025-01-17 Size : 37kb Publisher : Japerski
Basic_Examples Downloaded：0: Basic syntax and codes used in VHDL
Update : 2025-01-17 Size : 1kb Publisher : Japerski
cy4ex14 Downloaded：0: verilog fpga
Update : 2025-01-17 Size : 4.8mb Publisher : 姜晓明
VHDL-Design-of-31-bit-Pipelined-Adder Downloaded：0: The design runs at 316.46 MHz and uses 125 LEs.
Update : 2025-01-17 Size : 215kb Publisher : hooman hematkhah
8-bit-Multiplier Downloaded：0: Multiplication is performed in three stages. After reset, the 8-bit operands are “loaded” and the product register is set to zero. In the second stage, s1, the actual serial-parallel multiplication takes place. In the th
Update : 2025-01-17 Size : 189kb Publisher : hooman hematkhah
I2C Downloaded：0: Can fully realize the I2C, a detailed code notes, very easy to understand.
Update : 2025-01-17 Size : 6.86mb Publisher : glywhh
8-bit-Restoring-Divider Downloaded：0: Division is performed in four stages. After reset, the 8-bit numerator is “loaded” in the remainder register, the 6-bit denominator is loaded and aligned (by 2N− 1 for a N bit numerator), and the quotient register i
Update : 2025-01-17 Size : 224kb Publisher : hooman hematkhah

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