VHDL-FPGA-Verilog List Page 379

VHDL-FPGA-Verilog list

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full_adder_VHDLproject Downloaded：0: Update : 2025-01-18 Size : 1.6mb Publisher : xiaobei
half_adder_VHDLproject Downloaded：0: Update : 2025-01-18 Size : 1.42mb Publisher : xiaobei
mutex_3to8_VHDLproject Downloaded：0: Update : 2025-01-18 Size : 1.73mb Publisher : xiaobei
S6_VHDLproject Downloaded：0: Update : 2025-01-18 Size : 2.45mb Publisher : xiaobei
PIE Downloaded：1: PIE DECDODER decotes pulse interval encoding dignal of RFID tags. OUTPUT is serial bits and parallel register (128 width).
Update : 2025-01-18 Size : 5kb Publisher : harvanek
crc16 Downloaded：0: CRC 16 endcoder/ decoder. The source includes two modules. The first operates with 16 bit register. The second one operates with serial data.
Update : 2025-01-18 Size : 1kb Publisher : harvanek
crc5 Downloaded：0: CRC 5 encription and decription module. Operates with serial input data, CRC output is 5bits register. If you decoding CRC the input is valid when output is set to 00000 .
Update : 2025-01-18 Size : 1kb Publisher : harvanek
CRC Downloaded：0: CRC is to achieve the sequence information obtained 3bit the CRC generator polynomials take g (x) = X ^ 3+ X+ 1, corresponding to generate a sequence of 1011.
Update : 2025-01-18 Size : 4.05mb Publisher : WQ
07_number_mod Downloaded：0: 2 digital verilog language design tube drive. In Quarus11.0 compiler success, and OK in the test development board black gold
Update : 2025-01-18 Size : 5.62mb Publisher : hmyang2006
vga_driver Downloaded：0: verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK
Update : 2025-01-18 Size : 27.38mb Publisher : hmyang2006
sha1 Downloaded：0: Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.
Update : 2025-01-18 Size : 3kb Publisher : 谭清莉
DS28E01 Downloaded：0: Using Verilog language to achieve the encryption chip DS28E01 call operation commands.
Update : 2025-01-18 Size : 4kb Publisher : 谭清莉

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