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VHDL-FPGA-Verilog list
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my_cpu
Downloaded:0
Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4
Update
: 2025-01-18
Size
: 2.22mb
Publisher
:
李旭东
AlertLogPkg
Downloaded:0
osvvm alert packages that is helpful for vhdl verification
Update
: 2025-01-18
Size
: 13kb
Publisher
:
anupam maurya
CoveragePkg
Downloaded:0
osvvm coverage packages that is helpful for vhdl verification
Update
: 2025-01-18
Size
: 21kb
Publisher
:
anupam maurya
frequency-generation
Downloaded:0
Frequency divider based on VHDL language, input control four bits to produce the corresponding output frequency.
Update
: 2025-01-18
Size
: 3.2mb
Publisher
:
jianyong
traffic
Downloaded:0
Quartus II with a written two-way traffic lights running simulation ok, directly under the board
Update
: 2025-01-18
Size
: 1.36mb
Publisher
:
Wane
example19-LCD1602
Downloaded:0
Based verilog HDL of LCD1602 display program, debugging through, can be called directly.
Update
: 2025-01-18
Size
: 962kb
Publisher
:
lwb
example17-DS1302_ok
Downloaded:0
FPGA verilog HDL developed clock chip DS1302, debuggers are available.
Update
: 2025-01-18
Size
: 962kb
Publisher
:
lwb
example20-LCD12864
Downloaded:0
FPGA 12864 lcd driver, verilog HDL language development, it can be used directly.
Update
: 2025-01-18
Size
: 394kb
Publisher
:
lwb
example14-ADC-ok
Downloaded:0
Based verilog HDL developed ADC tlc549 control program has been adopted debugging.
Update
: 2025-01-18
Size
: 488kb
Publisher
:
lwb
VHDL_RAM_FIFO_ROM
Downloaded:0
VHDL code for FIFO read data ROM to RAM and then transfer
Update
: 2025-01-18
Size
: 9.19mb
Publisher
:
胡小军
Verilog-HDL
Downloaded:0
This compressed file package is very classic with Verilog hardware description language programs, there is a need friends can see.
Update
: 2025-01-18
Size
: 112kb
Publisher
:
西北野狼
ellip-(1)
Downloaded:0
Elliptic filter FPGA-based simulation using VHDL language quartus
Update
: 2025-01-18
Size
: 2.35mb
Publisher
:
aaa
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