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VHDL-FPGA-Verilog list
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Introduction to the Vivado Design Suite
Update : 2025-01-18 Size : 1.28mb Publisher : yin

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FPGA implementation of non-standard SPI bus to receive and decode the data, and to achieve ROM data read and
Update : 2025-01-18 Size : 5.75mb Publisher : zhlifeng0316

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8 piont 8 bits of FFT, verilog language, through the Quartus simulation
Update : 2025-01-18 Size : 4kb Publisher : liufeng

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Update : 2025-01-18 Size : 414kb Publisher : 黄绾力

additionneur code vhdl for fpga
Update : 2025-01-18 Size : 103kb Publisher : fifi

multiplixeur vhdl code for fpga
Update : 2025-01-18 Size : 106kb Publisher : fifi

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The program is mainly used Verilog HDL language multifunction digital clock, including at school, debugging, the whole point timekeeping and calendar modules.
Update : 2025-01-18 Size : 9kb Publisher : 林卡

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Sequence simulator, VHDL description to complete the state machine simulation
Update : 2025-01-18 Size : 106kb Publisher : 魏壑

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Reversing radar, can be completed in less than 3 meters distance and send different alert sound
Update : 2025-01-18 Size : 2.41mb Publisher : 魏壑

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Implement LED water lights Key Function Pause blinking
Update : 2025-01-18 Size : 403kb Publisher : 唐舒萍

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12/24 hour digital clock design, including the top-level VHDL design and VHDL source code file
Update : 2025-01-18 Size : 308kb Publisher :

Optional waveform signal generator VHDL design: sinusoidal (sine), square wave (sqr), sawtooth (jc_de and jc_in two kinds), triangle wave (sanj) and staircase (stair) signal modules
Update : 2025-01-18 Size : 741kb Publisher :
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