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VHDL-FPGA-Verilog list
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AD2548 SPI
Update : 2025-01-18 Size : 2kb Publisher : wei

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This written in VHDL digital logic circuit。It can realize the function of timing and by 23:59 to 00:00 conversion, has been in the FPGA test through!
Update : 2025-01-18 Size : 362kb Publisher : 李佳倩

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Based dspbuilder of fir filter design fpga Advanced Programming
Update : 2025-01-18 Size : 11.56mb Publisher : 程序猿

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Dsp builder based music player design FPGA and matlab joint programming
Update : 2025-01-18 Size : 2.03mb Publisher : 程序猿

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Custom real-time clock module-based design Qsys hardware design
Update : 2025-01-18 Size : 18.02mb Publisher : 程序猿

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vivado 7-BCD Digital display code。It can display four decimal digits. Enter the number of bits to modify.
Update : 2025-01-18 Size : 2kb Publisher : 汪汉森

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DDS signal source instance using Quartus II development environment
Update : 2025-01-18 Size : 972kb Publisher :

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Temperature sensor of a FPGA nexys 4 on verilog languaje
Update : 2025-01-18 Size : 334kb Publisher : Andruans

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Corresponding VHDL-based 4* 4 matrix identification keys, buttons and LED, each press of a button, the corresponding LED lights up again.
Update : 2025-01-18 Size : 5kb Publisher : 黄星

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Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development Quartus
Update : 2025-01-18 Size : 4.92mb Publisher : zhang

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The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be co
Update : 2025-01-18 Size : 203kb Publisher : gowtham

The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be co
Update : 2025-01-18 Size : 203kb Publisher : gowtham
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