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VHDL-FPGA-Verilog list
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From algorithm design to the realization of hardware logic (Xia Wen vreloge) Comparison of a classic book.
Update : 2025-01-16 Size : 2.26mb Publisher : 刘浩

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Manchester codec Verilog code very good speed, but also occupy less resources.
Update : 2025-01-16 Size : 10kb Publisher : 王鹏

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High-speed SDRAM controller, and provide simulation testing procedures and more detailed documents.
Update : 2025-01-16 Size : 415kb Publisher : yuhl

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A source EDA procedures, absolute certification. EDA suitable experimental boxes, and so on the basis of simulation experiment
Update : 2025-01-16 Size : 1.7mb Publisher : 杨之皓

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Commonly used classical typical circuit, such as the full adder, multiplier, how to reduce the resources
Update : 2025-01-16 Size : 4kb Publisher : 王鹏

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FPGA-based VGA display driver source code ~ for which you want to develop VGA interface driver friend
Update : 2025-01-16 Size : 1kb Publisher : 杨之皓

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Smart antenna adaptive LMS algorithm, the assumption that with four million antenna array.
Update : 2025-01-16 Size : 4kb Publisher : 黄虎

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RAKE receiver to achieve the maximal ratio combining criteria, enter the 16-bit wide.
Update : 2025-01-16 Size : 2kb Publisher : 黄虎

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The realization of a fourth-order and second slip parallel IIR filter.
Update : 2025-01-16 Size : 1kb Publisher : 黄虎

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Shift-by-code-based law 7 Barker Code focus on plug-in search algorithm.
Update : 2025-01-16 Size : 1kb Publisher : 黄虎

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Autoplay octave flower design VHDL source code, documentation, there are specific notes
Update : 2025-01-16 Size : 2kb Publisher : 黄利

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VHDL language used to write the procedure that contains the following functions: 1. Keyboard scan 2. Control of AD converters 3. Generate PWM signals with the 51 series CPU interface, and then in the address data bus 51,
Update : 2025-01-16 Size : 445kb Publisher : liubaogui
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