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VHDL-FPGA-Verilog list
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Based on the LS138 decoder VHDL realization of a very simple procedure
Update : 2025-01-29 Size : 91kb Publisher : philin

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Experiment IV Cymometer experimental requirements: design of an effective place for the 4 decimal digital frequency meter.
Update : 2025-01-29 Size : 133kb Publisher : 朱伟成

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Very good one on the Chinese Verilog Tutorial!
Update : 2025-01-29 Size : 2.79mb Publisher : 庞志远

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After four issues克鲁卡斯尔algorithm algorithms and concrete realization of algorithms, has been running before.
Update : 2025-01-29 Size : 1kb Publisher : 曾阿芷

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Verilog language in maxII series chip IIC function
Update : 2025-01-29 Size : 508kb Publisher : nedazq

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Verilog language in maxII the CPLD chip ps2 function source code
Update : 2025-01-29 Size : 468kb Publisher : nedazq

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Seven people vote in the voting process more than four does not pass through the less than four
Update : 2025-01-29 Size : 1kb Publisher : duzhifu

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vhdl. flower design. I am from somewhere under the. Please everyone pay attention to confidentiality.
Update : 2025-01-29 Size : 10kb Publisher : 朔夜

Verilog hdl North courseware! Internal information, including a large number of engineering practice, is to learn from the good information
Update : 2025-01-29 Size : 1.48mb Publisher : jackie

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Tsinghua University, verilog hdl code examples work, containing the source code, detailed documentation, very useful
Update : 2025-01-29 Size : 1.01mb Publisher : jackie

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8-bit CPU of the VHDL design, 16 instruction, as well as some of the test code, development tools is quartusii_60_pc
Update : 2025-01-29 Size : 3kb Publisher : FJ

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Electronic stopwatch, can display 0.01S to 59 59 99. With a moratorium, rehabilitation located in a key control functions.
Update : 2025-01-29 Size : 1kb Publisher : jacky
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