VHDL-FPGA-Verilog List Page 3970

VHDL-FPGA-Verilog list

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vhdlchengxuji Downloaded：0: Which contain a high level VHDL design source code, suitable for beginners to learn, and integrated design with the subject.
Update : 2025-01-16 Size : 14kb Publisher : 刘小霞
lcd Downloaded：0: Design entities: lcd driver- Color LCD chip LQ080V3DG01- original development board for Fiberxon UP-SOPC2000 development board to write the color LCD driver
Update : 2025-01-16 Size : 1.21mb Publisher : yanglijing
jianpan Downloaded：0: This is what I use Verilog language source matrix keyboard
Update : 2025-01-16 Size : 1kb Publisher : hejunbo
FPGA Downloaded：0: Senior FPGA teaching guide book experiment experimental platform- Embedded System Design
Update : 2025-01-16 Size : 412kb Publisher :
halfanderandander Downloaded：0: This is, respectively, with VHDL and Verilog language source code, inside also includes circuit devices generated map.
Update : 2025-01-16 Size : 386kb Publisher : hejunbo
tushuguan Downloaded：0: - Functional Description- 1 credit card and identity generated only the corresponding element of the serial binary code sequence, as a simulation system of the input signal (in this case may be set to No. 8 students).- 2
Update : 2025-01-16 Size : 1kb Publisher : leizi
61EDA_B307 Downloaded：0: Stepper Motor/DC Motor Controller Stepper Motor breakdown of rotation, with or without a breakdown rotation DC motor control
Update : 2025-01-16 Size : 114kb Publisher : 李宁
VerilogHDLSource Downloaded：0: Verilog HDL Design Tutorial matching source
Update : 2025-01-16 Size : 166kb Publisher : tmjdone
stepper_motor_control_design_example Downloaded：0: VHDL stepper motor control, whole-step half-step breakdown of the use of actel FPGA
Update : 2025-01-16 Size : 1.29mb Publisher : 李宁
FT245BM Downloaded：0: This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Update : 2025-01-16 Size : 953kb Publisher : 杨林成
sy Downloaded：0: Seven-Segment display decoder (functions: binary number will be thinking to seventh output signal, drive the digital display)
Update : 2025-01-16 Size : 4kb Publisher : snow
crc16_ccitt Downloaded：0: crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Update : 2025-01-16 Size : 3kb Publisher : 樊文杰

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