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This procedure is based on Verilog language program, the role is to eliminate keyboard shaking, digital display.
Update : 2024-12-23 Size : 2kb Publisher : 啊光

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About the LED of PWM
Update : 2024-12-23 Size : 3.11mb Publisher : xlxw

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1. Idle, which is the default state, is not responding to the test being executed. 2. This will inform users that a new reaction test is about to start. For example, users can notify the upcoming reaction test by countin
Update : 2024-12-23 Size : 1.6mb Publisher : zhexigua

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UART design based on FPGA
Update : 2024-12-23 Size : 5.73mb Publisher : 梦里千梦

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The simulation of CD4527(BCD proportional multiplier)
Update : 2024-12-23 Size : 2kb Publisher : 光速ZY

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verilog code for binary multiplier
Update : 2024-12-23 Size : 3.58mb Publisher : krisna

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The initial library file of Vivado contains 74LS series IP module and XUP series module.
Update : 2024-12-23 Size : 368kb Publisher : 李航16

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This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atly
Update : 2024-12-23 Size : 13.13mb Publisher : domnish

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USB2.0 based C++ upper computer, measured available, for reference only.
Update : 2024-12-23 Size : 23.62mb Publisher : feiyue324

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This program has completed the acquisition of dual data. Through the ad module, the analog data is converted into 12 bit digital signals and is sent to the serial port assistant at the PC side through the serial port.
Update : 2024-12-23 Size : 3.21mb Publisher : 张小er

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The SHA-1 main control module realizes the control of the whole SHA-1 process.
Update : 2024-12-23 Size : 1kb Publisher : anglo

The design of FPGA data acquisition program based on ADS8556.
Update : 2024-12-23 Size : 15kb Publisher : 小美玉
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