VHDL-FPGA-Verilog List Page 41

VHDL-FPGA-Verilog list

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FiniteStateMachine Downloaded：0: Finite State Machine based on VHDL
Update : 2024-12-23 Size : 114kb Publisher : richugh
12864 Downloaded：0: Through the C language, 51 single chip microcomputer is used to drive the 12864 LCD screen, so that it can display pictures.
Update : 2024-12-23 Size : 14kb Publisher : 啧啧啧ZZZ
31条CPUtest Downloaded：0: CPU test 31 cmd CPU testbench & testdata
Update : 2024-12-23 Size : 725kb Publisher : YUNA939
rtl Downloaded：0: Realization of AD7606 data acquisition
Update : 2024-12-23 Size : 17kb Publisher : 歌不尽江湖
实验2 Downloaded：0: Design a decimal adder with clock synchronization enable
Update : 2024-12-23 Size : 2.12mb Publisher : moemoechan
VGA Downloaded：0: Xilixnx FPGA drives 640*480 display to display red, green and blue stripe.
Update : 2024-12-23 Size : 3.99mb Publisher : abc...
音乐播放 Downloaded：0: To achieve buzzer music playing, using the timing interrupt output frequency.
Update : 2024-12-23 Size : 51kb Publisher : 主1
led Downloaded：0: Running water lamp experiment to realize the function of four bit flow lamp
Update : 2024-12-23 Size : 2.46mb Publisher : 小猪仔521
PLL Downloaded：0: The main task of this design is to learn to call the phase-locked loop IP core.
Update : 2024-12-23 Size : 213kb Publisher : 小猪仔521
yima3_8 Downloaded：0: The 3_8 decoder converts the input three bit code to 8 bit output, so that one of the bits is different from others, thus realizing the decoding function.
Update : 2024-12-23 Size : 2.89mb Publisher : 小猪仔521
FIFO Downloaded：0: FPGA FIFO example, reading and writing FIFO in FPGA chip.
Update : 2024-12-23 Size : 3.39mb Publisher : 小猪仔521
chuankou Downloaded：0: The UART loopback test example receives the UART data sent by the PC terminal, and the original data is returned to the PC terminal, that is, the loopback function.
Update : 2024-12-23 Size : 3.42mb Publisher : 小猪仔521

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