VHDL-FPGA-Verilog List Page 46

VHDL-FPGA-Verilog list

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FPGA设计指导准则 Downloaded：0: FPGA design guidelines
Update : 2024-12-23 Size : 2.84mb Publisher : gemini_amis
01_led_test Downloaded：0: the use of digital FPGA design flow to achieve the runing water lights function
Update : 2024-12-23 Size : 315kb Publisher : 董进宇
spi final Downloaded：0: verilog spi can be demonstrated with FPGA
Update : 2024-12-23 Size : 3.84mb Publisher : `m
分频器 Downloaded：0: realization of frequency division
Update : 2024-12-23 Size : 8kb Publisher : MATLAB难啊
FIR设计实现sgh Downloaded：0: FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.
Update : 2024-12-23 Size : 25kb Publisher : 韩冻少
sd_test Downloaded：0: SD card initialization, reading and writing, with FPGA based
Update : 2024-12-23 Size : 2.09mb Publisher : 芬达sy
SN7474 Downloaded：0: 74LS74 chip behavior level code
Update : 2024-12-23 Size : 562kb Publisher : superEason
FP_adder Downloaded：0: 32 bit floating point adder with testbench
Update : 2024-12-23 Size : 11kb Publisher : liki20
FP_divider Downloaded：0: floating point divider for 32 bit with test bench
Update : 2024-12-23 Size : 11kb Publisher : liki20
FP_multiplier Downloaded：0: Multiplier for 32 bit with test bench using verilog HDL
Update : 2024-12-23 Size : 11kb Publisher : liki20
PWN Downloaded：0: Pulse Width modulation using Verilog HDL
Update : 2024-12-23 Size : 6kb Publisher : liki20
ADC_SA_8bit Downloaded：0: the successive approximation part of the circuit. trial_root is loaded with value 8'b1000_0000 on the rising egde that makes count = 3'b000.
Update : 2024-12-23 Size : 7kb Publisher : liki20

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