VHDL-FPGA-Verilog List Page 35

VHDL-FPGA-Verilog list

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Clock Downloaded：0: This design realizes a digital clock design based on FPGA, uses the Verilog hardware description language to design the digital circuit, uses the top down method to decompose the circuit system layer by layer, and design
Update : 2024-12-23 Size : 3.66mb Publisher : 威威谈谈
jiaotongdeng_fuza Downloaded：0: Based on the development of FPGA technology and the development platform of Quartus II, the realization of traffic lights controller at intersection is a solution. The Verilog HDL hardware description language is used to
Update : 2024-12-23 Size : 5.35mb Publisher : 威威谈谈
eetop.cn_cordic_sqrt Downloaded：1: The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.
Update : 2024-12-23 Size : 1kb Publisher : 躲在岸上的鱼
CAN驱动器-MCP2515-接口程序-Verilog Downloaded：0: CAN driver MCP2515 driver, Verilog written, measured available
Update : 2024-12-23 Size : 9kb Publisher : 天下布狼
dds Downloaded：0: Fang Bo, sine wave, triangle wave and sawtooth wave at any frequency are generated by key control
Update : 2024-12-23 Size : 3.95mb Publisher : HUMBLE.
DBSTAR_RGMII Downloaded：0: Verilog implementation of RGMII and GMII interface transfer
Update : 2024-12-23 Size : 4.9mb Publisher : zhzp
RS(204,188)译码器的设计 Downloaded：2: RS (204188) decoder explanation Original document: Rs_decoder.v (top level file), SyndromeCalc.v (Computational adjoint), BM_KES.v (BM solving key equations). Forney.v (Forney algorithm for error sample), CheinSearch.v (
Update : 2024-12-23 Size : 15kb Publisher : HelloFrank0
ddc Downloaded：0: Detailed code and notes for down conversion sampling, local oscillator and filtering
Update : 2024-12-23 Size : 3kb Publisher : 樨卡
Verilog Downloaded：0: aes digital audio interface from xilinx
Update : 2024-12-23 Size : 48kb Publisher : SiamackBM
ldpc_decoder_802_3an Downloaded：0: The module of LDPC to implement the coding of the 802-3an protocol
Update : 2024-12-23 Size : 994kb Publisher : fengyuanzyt
中级篇03：UART，波特率115200与PC通信 Downloaded：0: This program implements the serial communication function of the FPGA, and can transmit digital characters, etc., and the baud rate is 115200.
Update : 2024-12-23 Size : 10.07mb Publisher : 小明d1
Altera+OpenCL Downloaded：0: Altera's OpenCL is mainly a client for signal processing applications, a tool for developing FPGA in the C language. The famous companies in the open computing language (OpenCL) alliance are FPGA giant Altera, two big ca
Update : 2024-12-23 Size : 457kb Publisher : CrazyICer

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