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VHDL-FPGA-Verilog list
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encode and decode program with MD5
Update : 2024-12-23 Size : 52kb Publisher : featrick

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SOPC development, user custom instruction, teach you to learn SOPC, absolutely useful
Update : 2024-12-23 Size : 6.2mb Publisher : 岳天宇

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CPU interrupt mask handling.
Update : 2024-12-23 Size : 1kb Publisher : czpiugd

VHDL design with a fir-order low-pass filter 18 documents
Update : 2024-12-23 Size : 5kb Publisher : sherry wang

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S3C24XX CPU Frequency scaling - debugfs status support.
Update : 2024-12-23 Size : 6kb Publisher : ponkmin

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Leds flashing.
Update : 2024-12-23 Size : 313kb Publisher : Whiteside

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thisis a xilinx_PCIeLogiCore
Update : 2024-12-23 Size : 4.31mb Publisher : laughing110

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Jitter Test Program Jitter Test
Update : 2024-12-23 Size : 31kb Publisher : mehack

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Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed
Update : 2024-12-23 Size : 4.19mb Publisher : 王远震

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Quartus HDLC codec under development include design documentation and reports, by RTL and timing simulation
Update : 2024-12-23 Size : 6.57mb Publisher : 王远震

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Simple calculator 4* 4 matrix keyboard input, multiple values vhdl codes
Update : 2024-12-23 Size : 12kb Publisher : 刘飞

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patterns programs in the language c
Update : 2024-12-23 Size : 1kb Publisher : pace
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