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TR4_GPIO1_D8M
Downloaded:0
The development board of TR4, the D8M camera program. The output is the 10 bit data after MIPI decoding. include signaltap simulation results and connection diagrams
Update
: 2024-12-22
Size
: 27.49mb
Publisher
:
xttttttT
MVB通信架构和流程图
Downloaded:1
MVB development, Dalian Haitian data
Update
: 2024-12-22
Size
: 403kb
Publisher
:
湖南秋秋
systemverilog+assertions应用指南
Downloaded:0
system verilog assertion introduction
Update
: 2024-12-22
Size
: 1.23mb
Publisher
:
foreverleej
Quartus_18.0_破解器_Windows密码12345
Downloaded:1
Quartus_18.0_crack_Windows,password:12345
Update
: 2024-12-22
Size
: 106kb
Publisher
:
YoucanBaby
teacher_uart
Downloaded:0
The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3
Update
: 2024-12-22
Size
: 1.84mb
Publisher
:
abc1997
Xilinx_FPGA-macro-use
Downloaded:1
The use of Xilinx FPGA bottom macrocell is very detailed and suitable for basic entry learning.
Update
: 2024-12-22
Size
: 701kb
Publisher
:
CrazyICer
基于FPGA的负延迟设计
Downloaded:1
FPFA based negative delay design written in VHDL language
Update
: 2024-12-22
Size
: 150kb
Publisher
:
守候在街口
DDR_sdram
Downloaded:0
The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.
Update
: 2024-12-22
Size
: 4.71mb
Publisher
:
maxw123456789
Quartus_17.1破解器_Windows_密码12345
Downloaded:0
Quartus 17.1 installation kit, what I am using now is
Update
: 2024-12-22
Size
: 107kb
Publisher
:
梦里千梦
emmc
Downloaded:7
The implementation code of EMMC protocol
Update
: 2024-12-22
Size
: 10kb
Publisher
:
TJJ14520
xapp495(1)
Downloaded:0
Implement HDMI interface 1.0, including receiver and transmitter,from Xilinx xapp
Update
: 2024-12-22
Size
: 47kb
Publisher
:
likaiyi
FIFO_UVM
Downloaded:1
this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output
Update
: 2024-12-22
Size
: 226kb
Publisher
:
gana123
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