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VHDL-FPGA-Verilog list
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A Binary Operator and Digital Tube Scanning Display Circuit for EDA Homework of Digital Electronic Technology Course of Tsinghua University
Update : 2024-12-22 Size : 33kb Publisher : jameskk

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SRAM 8K*8 Chip memory Chip memory
Update : 2024-12-22 Size : 3kb Publisher : 1234556 去啊

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51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE
Update : 2024-12-22 Size : 2kb Publisher : Vicky2008

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The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.
Update : 2024-12-22 Size : 656kb Publisher : DGP1997

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Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering
Update : 2024-12-22 Size : 14.35mb Publisher : Andy1123

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Module function: to eliminate chromatic aberration (green fog) caused by illumination through white balance. Module input: brightness gain output R, G, B three channel pixel value (double) Module output: white balance af
Update : 2024-12-22 Size : 1kb Publisher : Andy1123

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UART send and receive verilog code, including verilog source code, testbench etc.
Update : 2024-12-22 Size : 442kb Publisher : 66778899

Pi4 QPSK's paid papers will be very useful for FPGA.
Update : 2024-12-22 Size : 504kb Publisher : Haiton

Eagle DataSheet v1.9 - EG4X20BG256
Update : 2024-12-22 Size : 3.48mb Publisher : rotzeimer

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Including address generation unit, data query unit (data can be re-initialized in rom, generated by matlab. COE file replacement), integration unit, extraction unit, comb filter unit, is very helpful for beginners.
Update : 2024-12-22 Size : 5kb Publisher : 午后河流

A single cycle CPU written in Verilog for group experiment.
Update : 2024-12-22 Size : 9kb Publisher : RogerBryant

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The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed
Update : 2024-12-22 Size : 4kb Publisher : 力力力123
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