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VHDL-FPGA-Verilog list
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library
Downloaded:0
VHDL introduction of library calls, so call for the Treasury have a deeper understanding of
Update
: 2025-01-16
Size
: 3kb
Publisher
:
chenwen
shinengcount
Downloaded:0
Band so that
Update
: 2025-01-16
Size
: 1kb
Publisher
:
chenwen
binarycount
Downloaded:0
Asynchronous reset, synchronous purchase the number of binary counter 4 of the VHDL source files
Update
: 2025-01-16
Size
: 1kb
Publisher
:
chenwen
intcount
Downloaded:0
Realize the four forms with integer addition, a source counters
Update
: 2025-01-16
Size
: 1kb
Publisher
:
chenwen
CPLD_raoma
Downloaded:0
CPLD based on the scrambling code and Descrambling codec design, scrambling code sequence with M realize, m sequence of series and frequency optional
Update
: 2025-01-16
Size
: 39kb
Publisher
:
梁奔山
niosII_minu_system
Downloaded:0
Nios nuclear entry of the tutorial to use the simplest, one school will be, painless entry.
Update
: 2025-01-16
Size
: 903kb
Publisher
:
梁奔山
alteraexample
Downloaded:0
CPLD/FPGA module with commonly used integrated system design example CD-ROM program
Update
: 2025-01-16
Size
: 16.65mb
Publisher
:
徐
dds_good
Downloaded:0
The use of DDS technology waveform generator, FPGA realization.
Update
: 2025-01-16
Size
: 499kb
Publisher
:
fir
Downloaded:1
VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you t
Update
: 2025-01-16
Size
: 888kb
Publisher
:
王志
generalFIFO
Downloaded:0
General FIFO's VHDL programming word depth and word length can be designed by itself
Update
: 2025-01-16
Size
: 1kb
Publisher
:
danny
FPGA_design
Downloaded:0
Video controller FPGA design, FED-driven control system design and FPGA
Update
: 2025-01-16
Size
: 1.94mb
Publisher
:
雅兰
080513154000
Downloaded:0
Parallel to serial VHDL description: Based on the FPGA to send the SPI module
Update
: 2025-01-16
Size
: 93kb
Publisher
:
yaoqinghua
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4311
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