VHDL-FPGA-Verilog List Page 4010

VHDL-FPGA-Verilog list

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50vvoltmeter Downloaded：0: Through an external keyboard to the system reset control and display stalls to choose, different stalls choose a different input voltage range (0 ~ 5,5 ~ 50). (1) control part: Using FPGA for the control of the core (2)
Update : 2025-01-15 Size : 135kb Publisher : 丁珊珊
csma030390 Downloaded：0: Simulation of Ethernet frames sent process, so that readers familiar with the Ethernet data frames to send flow
Update : 2025-01-15 Size : 1kb Publisher : 猪八戒
seg7_1 Downloaded：0: Using VHDL description of a six digital tube display controller at the same time, also showed that six different 0,1,2,3,4,5 digital graphics to six digital tube, the input clock frequency adjustment, making it possible
Update : 2025-01-15 Size : 1kb Publisher : wx
zmd_1 Downloaded：0: Use VHDL to describe an 8-digit LED lantern. System has reset. Single point of mobile model: a point in eight light-emitting diode on the light back and forth. Curtain-style: from between the two points, at the same time
Update : 2025-01-15 Size : 1kb Publisher : wx
zmd_1 Downloaded：0: Use VHDL to describe an 8-digit LED lantern. System has reset. Single point of mobile model: a point in eight light-emitting diode on the light back and forth. Curtain-style: from between the two points, at the same time
Update : 2025-01-15 Size : 1kb Publisher : wx
vhdl Downloaded：0: Digital phase-measuring instrument, based on the FPGA digital phase-measuring instrument production
Update : 2025-01-15 Size : 23kb Publisher : 郑淑琴
DPLL_verilog Downloaded：0: First-order DPLL VERLOGIC program code, debugging through.
Update : 2025-01-15 Size : 2kb Publisher : 梁大法
DIGTAL_FIR Downloaded：0: Loop filter design, FPGA-based PLL applications.
Update : 2025-01-15 Size : 756kb Publisher : 梁大法
100_vhdl_example Downloaded：0: The book introduced the 100 applicable to VHDL source code, and have simulation graph.
Update : 2025-01-15 Size : 6.63mb Publisher : 梁大法
eecadd_8 Downloaded：0: This procedure using VHDL language, in the four adder based on the completion of eight binary adder, the output is BCD code
Update : 2025-01-15 Size : 192kb Publisher : 韩善华
add_32_bcd Downloaded：0: This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
Update : 2025-01-15 Size : 1kb Publisher : 韩善华
fft_test Downloaded：0: FFT prepared using VHDL code, it is wide, it is powerful.
Update : 2025-01-15 Size : 891kb Publisher : fangyingjie

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