VHDL-FPGA-Verilog List Page 4015

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .10 .11 .12 .13 .14 4015.16 .17 .18 .19 .20 ... 4311 »

VerilogSDRAMcontry Downloaded：0: This document is a basic principle of SDRAM discussed using VERILOG language!
Update : 2025-01-15 Size : 4kb Publisher : JP
I2CVHDL Downloaded：0: The i2c VHDL procedures, has been simulated and can be successfully applied correctly
Update : 2025-01-15 Size : 38kb Publisher : 张海风
NL_prsg9 Downloaded：0: VHDL pseudo-random sequence launchers procedures, has been simulated and can be successfully applied correctly
Update : 2025-01-15 Size : 1kb Publisher : 张海风
LCD1602 Downloaded：0: LCD1602 display the source code 1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the function of the procedure is a standard 16 × 2 character LCD module to display
Update : 2025-01-15 Size : 700kb Publisher : 张海风
PS2_RS232 Downloaded：0: Realize PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and reception area in the data show receive char
Update : 2025-01-15 Size : 1.34mb Publisher : 张海风
PS2_LCD Downloaded：0: Ps /2 keyboard input, display ASCII code through led 2. Wait for 1s to display the entered characters on the LCD
Update : 2025-01-15 Size : 336kb Publisher : 张海风
DTXS Downloaded：0: Verilog HDL, prepared by four digital tube dynamic display procedures, the external circuit with CPLD to realize
Update : 2025-01-15 Size : 1kb Publisher : yangytp
m Downloaded：0: Answer four devices, the use of FPGA development tools, can be run directly on your computer, but I want to use the combination of hardware
Update : 2025-01-15 Size : 141kb Publisher : pan
vhdl_lcd_success Downloaded：0: Based on the DE2 board, Quartus6.0 development environment, drive a two-line LCD, which can set the frequency value of the even smaller number, debug successfully, the compiler can be downloaded.
Update : 2025-01-15 Size : 275kb Publisher : tallergao
Verilog Downloaded：0: Verilog Digital System Design Course (Summer in the smell)
Update : 2025-01-15 Size : 3.23mb Publisher : 宋振丰
crccode Downloaded：0: CRC cyclic redundancy test Verilog coding procedures
Update : 2025-01-15 Size : 1kb Publisher : yuanxiaonan
QUARTUSII-FPGA Downloaded：0: Quartus FPGA development make use of the entire flow for beginners
Update : 2025-01-15 Size : 1.27mb Publisher : s.y

« 1 2 ... .10 .11 .12 .13 .14 4015.16 .17 .18 .19 .20 ... 4311 »

Search in result