VHDL-FPGA-Verilog List Page 4012

VHDL-FPGA-Verilog list

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sji Downloaded：0: Taxi fees charged, and can realize a taxi start-up, pause, remember when the fees and features in mind.
Update : 2025-01-15 Size : 2kb Publisher : 空军
1253 Downloaded：0: Based on the VHDL language taxi billing system design, developed in muxplus realize. Realize the basic entry fee taxi Developer
Update : 2025-01-15 Size : 196kb Publisher : 空军
lift_controler-verilog Downloaded：0: Using Verilog to write elevator controller, containing the test documentation and test reports
Update : 2025-01-15 Size : 650kb Publisher : jia
DM74LS163soursecode Downloaded：0: QurtursII platform using DM74LS163 chip simulation
Update : 2025-01-15 Size : 1.49mb Publisher : soul
motorcontrol_cpld Downloaded：0: EPM570 in ALTERA
Update : 2025-01-15 Size : 1.12mb Publisher : Xinzhong.Ding
fifo8_8 Downloaded：0: 8* 8 of the fifo data buffer of the VHDL source code. After quartus ii 6.0 proved to be successful.
Update : 2025-01-15 Size : 1kb Publisher : 李松
clock_design Downloaded：0: Digital Clock in Verilog code, quartusII development environment.
Update : 2025-01-15 Size : 405kb Publisher : 屈开
16bitadder Downloaded：0: The 16-bit fast adder verilong is well worth seeing
Update : 2025-01-15 Size : 3kb Publisher : 屈开
DDSverilogsource Downloaded：0: DDS of the Verilog source code, please support the U.S. more than
Update : 2025-01-15 Size : 3kb Publisher : 屈开
DM9000A_IPcose Downloaded：0: Such as the title: dm9000aIP nuclear, after verification, can be used
Update : 2025-01-15 Size : 17kb Publisher : yt
sine Downloaded：0: Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Update : 2025-01-15 Size : 4.57mb Publisher : 陈剑
DDS-320-modu Downloaded：0: 320x240 screen using the design of experiments to run me generate sine wave, AM FM waveforms, sweep.
Update : 2025-01-15 Size : 1.19mb Publisher : hangyinli

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