VHDL-FPGA-Verilog List Page 4088

VHDL-FPGA-Verilog list

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cnt10 Downloaded：0: VHDL-based 10-band counter module, to achieve 0-9 count
Update : 2025-01-12 Size : 23kb Publisher : 贝凯
dds_8bit Downloaded：0: rom address the width of 8, 256 sine wave data. Frequency control word can step has cleared function.
Update : 2025-01-12 Size : 344kb Publisher : eroad
dianzi_vhdl Downloaded：0: Advanced electronic technology EDA part of a dds within the VHDL code, I make reference to the code, achieved a 10 and 8 of the dds, in EPF10K10TC144-4 chip verification through.
Update : 2025-01-12 Size : 183kb Publisher : eroad
gwdvpb Downloaded：0: The use of precision measuring principle, the use of VHDL programming through the FPGA to design a digital frequency meter design with high practicality and reliability of
Update : 2025-01-12 Size : 1kb Publisher : tangjia
CEU Downloaded：0: Verilog programming channel estimation, the program development environment for Xilinx ISE7.1
Update : 2025-01-12 Size : 3kb Publisher : chuzhaocai
trafficwsdklk Downloaded：0: 1. Designed to (1) design of traffic signal controllers (2) study the design method of state machine (3) learning principle diagram, state machine design methods such as mixed design (4) proficiency in the design of inpu
Update : 2025-01-12 Size : 129kb Publisher : 秦光
sdram_inf Downloaded：0: SDRAM operation of VHDL source code, the preparation of their own nuclear SDRAM have a good reference value
Update : 2025-01-12 Size : 2kb Publisher : 宋军
MAX_UFM Downloaded：0: Altera epm240 the UFM call.
Update : 2025-01-12 Size : 221kb Publisher : Potossas
8051-vhdl-code Downloaded：0: Singlechip 8051 IP core VHDL source code, the need for development environment QUARTUS II 6.0.
Update : 2025-01-12 Size : 96kb Publisher : 周华茂
6-portRegisterFile Downloaded：0: 6-port register IP core VHDL source code, required for the development environment is QUARTUS II 6.0.
Update : 2025-01-12 Size : 28kb Publisher : 周华茂
BIST_Circuits Downloaded：0: BIST circuits IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Update : 2025-01-12 Size : 5kb Publisher : 周华茂
SoC_WishboneSystem Downloaded：0: SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Update : 2025-01-12 Size : 89kb Publisher : 周华茂

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