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VHDL-FPGA-Verilog list
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Xilinx design and complete a 10-bit D/F converter, the digital input from the keys K1, K2 to regulate, including the completion of plus 1 functions K1, K2 and completed by 1 functions, and to convert the structure of the
Update : 2025-01-12 Size : 78kb Publisher : haolj

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Xilinx to achieve the use of a simple flower. Numbered musical notation of the musical alphabet and frequency-one correspondence.
Update : 2025-01-12 Size : 123kb Publisher : haolj

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The UART reference design band cache is used for Xinlix for fpga-uart reference design with cache for Xinlix for FPGA
Update : 2025-01-12 Size : 273kb Publisher : sd

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Based on c language source SD card reader, I hope all of you to help ~
Update : 2025-01-12 Size : 20kb Publisher : 王一木

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Signal generator by the waveform selector switch to control the output waveform, respectively, to the output sine wave, square and triangular waveforms in three waves, waveform cycle for 2 seconds
Update : 2025-01-12 Size : 1kb Publisher : 王军

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vcs tutorial lab1, very good
Update : 2025-01-12 Size : 6kb Publisher : 王一木

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vcs tutorial Lab2-PLI verygood
Update : 2025-01-12 Size : 4kb Publisher : 王一木

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Using Verilog to achieve the electronic calendar program, compiled in the Quartus II and successfully achieved through
Update : 2025-01-12 Size : 647kb Publisher : 张兵

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Realized by Verilog program in mind when, in the Quartus II compiled and successfully run through
Update : 2025-01-12 Size : 2.12mb Publisher :

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Answer realized by Verilog program, compiled in the Quartus II and successfully run through
Update : 2025-01-12 Size : 186kb Publisher :

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Prepared using Verilog 32 alu parts, used cpu production
Update : 2025-01-12 Size : 3kb Publisher : 胡豫陇

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Digital clock display module, using the realization of VERILOG HDL
Update : 2025-01-12 Size : 11kb Publisher : liufanyu
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