VHDL-FPGA-Verilog List Page 4091

VHDL-FPGA-Verilog list

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alaw_mulaw Downloaded：0: This is a quantization coding of them on the A law and u law compression and expansion of the source code, the program by VerilogHDL languages, algorithms in the ModelSim simulation have been carried out
Update : 2025-01-12 Size : 61kb Publisher : 刘柳
Mc68000 Downloaded：0: Mc68000 rtl code Simulation and Synthesis
Update : 2025-01-12 Size : 31kb Publisher : 李晓媛
vpr_430 Downloaded：0: FPGA design evaluation software for FPGA designers very helpful
Update : 2025-01-12 Size : 810kb Publisher : charles
pci144_vhdl Downloaded：0: PCI vhdl for Fpga designer to design PCI IP
Update : 2025-01-12 Size : 3kb Publisher : 李晓媛
Pcit32vhdl Downloaded：0: PCI 32 target IP for Fpga/asic Designer
Update : 2025-01-12 Size : 418kb Publisher : 李晓媛
mstr_mem32 Downloaded：0: Master MemoryExamples for MT32 v1.0.0 Rtl core
Update : 2025-01-12 Size : 29kb Publisher : 李晓媛
pci_express_crc Downloaded：0: PCI express CRC rtl core for Fpga/asic Designer
Update : 2025-01-12 Size : 198kb Publisher : 李晓媛
zyj Downloaded：0: Contains the main function of the electronic clock, input CLK for 1KHZ, output for the dynamic scan 8 CLD show. There are alarm, on-time time, time to adjust. Adjustment can display flashes. The clock for the 24-hour clo
Update : 2025-01-12 Size : 5kb Publisher : zyj
VHDL Downloaded：0: , Directed and written in VHDL code, for the realization of full-adder function, may have mistaken
Update : 2025-01-12 Size : 4kb Publisher : 金嘉
spi.tar Downloaded：0: SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Update : 2025-01-12 Size : 114kb Publisher : hcjian
uart_vhdl Downloaded：0: asynchronous serial VHDL code, can easily result in different FPGA in
Update : 2025-01-12 Size : 18kb Publisher : 李冰
pll Downloaded：0: pll clock in the FPGA to achieve the source code, can be realized or sub-octave frequency
Update : 2025-01-12 Size : 3kb Publisher : 张恒

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