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VHDL-FPGA-Verilog list
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USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
Update : 2025-01-08 Size : 189kb Publisher : 里晓军

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"digital circuit EDA portal-VHDL program examples"-- traffic lights procedures example
Update : 2025-01-08 Size : 3kb Publisher : 张文

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car taillight control system controller car taillight VHDL program
Update : 2025-01-08 Size : 2kb Publisher : 张文

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using VHDL prepared by the LED display driver circuit design source
Update : 2025-01-08 Size : 3kb Publisher :

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SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
Update : 2025-01-08 Size : 12kb Publisher : 曹大壮

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verilog 32-bit ALU
Update : 2025-01-08 Size : 2kb Publisher : qwasqwas

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this program is written in VHDL, including the AD0809, dual-port RAM, and other procedures. Debugging has been too
Update : 2025-01-08 Size : 4kb Publisher : lm

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This is the C language on the preparation of the 8051 VHDL source code
Update : 2025-01-08 Size : 385kb Publisher : 毕晓宇

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primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success in the compiler, Modelsim SE with six successful simulati
Update : 2025-01-08 Size : 1kb Publisher : jevidyang

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mcs51 the vhdl IP core, each is a must to learn FPGA, hoping to explore together
Update : 2025-01-08 Size : 385kb Publisher : bluebluewind

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modelsim designed adjustable duty cycle of the square wave program
Update : 2025-01-08 Size : 1kb Publisher : yanfei

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This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside the N and counter can be amended
Update : 2025-01-08 Size : 645kb Publisher : magma1981
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