VHDL-FPGA-Verilog List Page 4190

VHDL-FPGA-Verilog list

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ml50x_schematics Downloaded：0: xilinx company virtex-5 development board schematics can download look you want to help
Update : 2025-01-08 Size : 610kb Publisher : 王二
VHDL_Development_Board_Sources Downloaded：0: which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selector
Update : 2025-01-08 Size : 4.43mb Publisher : Jawen
clk_gen_translate Downloaded：0: this program different clock frequencies to the formation and transformation
Update : 2025-01-08 Size : 2kb Publisher : 李铭
calcu_synthesis Downloaded：0: the program two integers and the sum of squared output
Update : 2025-01-08 Size : 3kb Publisher : 李铭
prssdoc Downloaded：0: VHDL code based on the cultural code useful but may be under the wrong heart is dumping
Update : 2025-01-08 Size : 2kb Publisher : 轩辕李
sixuanyi Downloaded：0: four elected a selector, the importation of four, Output 1. When NM = 00 A at the election when NM = 01 am when the election NM B = C 10:00 when the election NM = 11:00 election D
Update : 2025-01-08 Size : 13kb Publisher : 赵总令
yiwei Downloaded：0: Bomadeng-shift register is a six lights, without delay entity
Update : 2025-01-08 Size : 1kb Publisher : 123
data_transfer Downloaded：0: synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal
Update : 2025-01-08 Size : 544kb Publisher : chengp
PCM30 Downloaded：0: SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register i
Update : 2025-01-08 Size : 836kb Publisher : chengp
TOKEN_vrilog Downloaded：0: synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal
Update : 2025-01-08 Size : 355kb Publisher : chengp
jurbojtag Downloaded：0: turbo jtag CPLD source code use altera EPM7 128S
Update : 2025-01-08 Size : 2kb Publisher : z8848
key_prog Downloaded：0: easy-to-read 4* 4 keyboard and display program. To the preparation of other forms of keyboard scan procedures are certain guiding significance.
Update : 2025-01-08 Size : 140kb Publisher : xht

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