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VHDL-FPGA-Verilog list
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ELEC_LOCK
Downloaded:0
four electronic password lock with a keyboard scan button shake, LCD driver encryption
Update
: 2024-12-24
Size
: 2kb
Publisher
:
xf
USB枚举
Downloaded:0
Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
Update
: 2024-12-24
Size
: 35kb
Publisher
:
xf
LCD显示实验
Downloaded:0
Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
Update
: 2024-12-24
Size
: 35kb
Publisher
:
xf
SRAM@DMA实验
Downloaded:0
Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Update
: 2024-12-24
Size
: 33kb
Publisher
:
xf
SPI接口音频Codec实验
Downloaded:0
Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Update
: 2024-12-24
Size
: 34kb
Publisher
:
xf
frequency发生器
Downloaded:0
A frequency generator wirriten by VHDL, which can generate different frequecies.
Update
: 2024-12-24
Size
: 1kb
Publisher
:
xf
verilog hdl教程135例
Downloaded:0
Easy and simple VerilogHDL programs to help you to get to the language quickly.
Update
: 2024-12-24
Size
: 155kb
Publisher
:
陈浩东
ASKDASK
Downloaded:0
ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
Update
: 2024-12-24
Size
: 94kb
Publisher
:
we
FSKDFSK
Downloaded:1
FSK modulation and demodulation, this procedure has been verified and can use communications students can use
Update
: 2024-12-24
Size
: 3kb
Publisher
:
we
lg
Downloaded:0
they simply based on the logic analyzer can show that the Eighth Route Army waveform, real-time waveform analysis of the Eighth Route Army
Update
: 2024-12-24
Size
: 1kb
Publisher
:
洪强
基于FPGA的李沙育图形发生器
Downloaded:0
This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Update
: 2024-12-24
Size
: 773kb
Publisher
:
孔玉
32位-33M 从模式(target)PCI接口参考设计_lattice
Downloaded:1
32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Update
: 2024-12-24
Size
: 807kb
Publisher
:
陈旭
«
1
2
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.53
.54
.55
.56
.57
4258
.59
.60
.61
.62
.63
...
4311
»
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