VHDL-FPGA-Verilog List Page 4260

VHDL-FPGA-Verilog list

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dsfs Downloaded：0: scan signal from C0 to C3 into the signal in order of 1000-gt; 0100- gt; 0010- gt; 0001- gt; 1000 cycle, when the scanning signal to 1000, then scanning 0 line of four keys. Scanning signal for 0100, then scanning resolu
Update : 2024-12-24 Size : 110kb Publisher : 杨要强
单片机坐标定时器实验 Downloaded：0: 7topic http://www.edacn.net/cgi-bin/forums.cgi forum = = 9127, under R3 R0 to the output signal will be one to one, but we are unable to confirm which a key is pressed, we must proceed from R3 to R0 the output signal C0
Update : 2024-12-24 Size : 1.49mb Publisher : 杨要强
mp3if Downloaded：0: through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasions.
Update : 2024-12-24 Size : 1kb Publisher : hcguan
I2C总线控制器 Xilinx提供 Downloaded：0: I2C bus contrll functions implemented by Verilog HDL.
Update : 2024-12-24 Size : 869kb Publisher : 司法
lightW Downloaded：0: a small LCD lights procedures. I did not write. I am only responsible for the debugging. Apply in ACEXEP1K30QC208-3 on. I run a simulator, marking the connecting pin. I next tried in a circuit board, there is no problem.
Update : 2024-12-24 Size : 231kb Publisher : 鄧翀
intro_to_quartus2_chinese Downloaded：0: A Chinese introduction to quartus II.
Update : 2024-12-24 Size : 2.95mb Publisher : 石峰
Figure_Models Downloaded：0: James Armstrong VHDL Design , source code
Update : 2024-12-24 Size : 45kb Publisher : 真名
des-verilog Downloaded：1: des encryption algorithm to achieve the Verilog language
Update : 2024-12-24 Size : 66kb Publisher : 杨云丰
clock_time Downloaded：0: this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
Update : 2024-12-24 Size : 1kb Publisher : 阿兰
示例（vhdl） Downloaded：0: VHDL examples examples to learn VHDL programming
Update : 2024-12-24 Size : 76kb Publisher : joan
UART设计参考 Downloaded：0: software designers Watchable UART reference design
Update : 2024-12-24 Size : 93kb Publisher : joan
ClkScan Downloaded：0: This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC)
Update : 2024-12-24 Size : 896kb Publisher :

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