VHDL-FPGA-Verilog List Page 4259

VHDL-FPGA-Verilog list

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qdq_new Downloaded：0: Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divide is three parts: The sampling electric
Update : 2024-12-24 Size : 64kb Publisher :
second&clk Downloaded：0: Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes
Update : 2024-12-24 Size : 329kb Publisher :
Music_altera Downloaded：0: Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
Update : 2024-12-24 Size : 637kb Publisher :
SPI串口的内核实现spicore Downloaded：0: SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore
Update : 2024-12-24 Size : 6kb Publisher : lfq
cpld_bus Downloaded：0: CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
Update : 2024-12-24 Size : 213kb Publisher : hamlemon
Convolutional encoding and Viterbi decoding with k Downloaded：0: convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Update : 2024-12-24 Size : 248kb Publisher : 周小川
4x4的数据选择器 Downloaded：0: 4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to learn.
Update : 2024-12-24 Size : 3kb Publisher : roya
pci 的vhdl 源代码 Downloaded：0: The source code of PCI VHDL.
Update : 2024-12-24 Size : 3kb Publisher : 陈旭
SECLOCK Downloaded：0: from a book copied but with the MAX PLUSII compile some of the problems beginners forgiven
Update : 2024-12-24 Size : 4kb Publisher : male
STUDY_CPLD.RAR Downloaded：0: This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.
Update : 2024-12-24 Size : 1.61mb Publisher : 开心火
65filter Downloaded：0: 65 FIR digital filter design ~ ~ with simulation data to come in through the importation of data from experiments completed filtering of the digital filter in the whole algorithm analysis including input a sum then multi
Update : 2024-12-24 Size : 3kb Publisher : 凌燕
t80 Downloaded：0: Configurable cpu core that supports Z80, 8080 and gameboy instruction sets
Update : 2024-12-24 Size : 41kb Publisher : 吴毅

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