VHDL-FPGA-Verilog List Page 4267

VHDL-FPGA-Verilog list

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标准的串口通讯设计VHDL Downloaded：0: communication design programme of standard asynchronous serial port base on VHDL programme
Update : 2024-12-23 Size : 10kb Publisher : 于飞
结合XILINXCPLD RS232通信(verilog) Downloaded：0: XILINXCPLD combine the simulation RS232 communication Verilog source
Update : 2024-12-23 Size : 119kb Publisher : 于飞
能综合的YCrCb2RGB模块（verilog)_采用3级流水线 Downloaded：0: can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
Update : 2024-12-23 Size : 1kb Publisher : 于飞
verilog SDRAM core Downloaded：1: I used to write Verilog HDL source of SDRAM core, the test application
Update : 2024-12-23 Size : 27kb Publisher : 于飞
Xilinx公司网站下的SDRAM Controller的参考设计 Downloaded：0: Xilinx website of SDRAM Controller reference design, validated
Update : 2024-12-23 Size : 125kb Publisher : 于飞
35_486_bus Downloaded：0: Please note : The cases include the description of the source file type, version of the study can not be compiled and simulation, if you need to compile this description and simulation, Beijing Polytechnic University and
Update : 2024-12-23 Size : 6kb Publisher : 撒旦
8位数字频率计 Downloaded：0: digtal frequency tester (use vhdl) can be used to test frequency (8bit)
Update : 2024-12-23 Size : 642kb Publisher : 熊明
uart from opencores Downloaded：0: VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Update : 2024-12-23 Size : 9kb Publisher : 熊明
xsoc-beta-093 Downloaded：0: This free cpu-ip! use verilog
Update : 2024-12-23 Size : 3.19mb Publisher : 王军
mealy FSM Downloaded：0: mealy Fsm and moore Fsm
Update : 2024-12-23 Size : 1kb Publisher : scy
Cadence_manual_1.2 Downloaded：0: Cadence_manual_1.2.pdf
Update : 2024-12-23 Size : 1.23mb Publisher : huyongming
config_controller Downloaded：0: VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.
Update : 2024-12-23 Size : 373kb Publisher : lsd

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