VHDL-FPGA-Verilog List Page 4271

VHDL-FPGA-Verilog list

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i2c_cores Downloaded：0: IIC bus protocol, VHDL language can be used directly
Update : 2024-12-23 Size : 20kb Publisher : 李无志
manchester_verilog Downloaded：0: manchesite time coding, VERILOG language, VHDL I find a site in a posting
Update : 2024-12-23 Size : 9kb Publisher : 李无志
alu Downloaded：0: hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.
Update : 2024-12-23 Size : 1kb Publisher : 江浩
idec Downloaded：0: 2. You may use this core in any way, be it academic, commercial, or-- military. Modified or not.
Update : 2024-12-23 Size : 2kb Publisher : 江浩
regs Downloaded：0: 3. Distribution of this core must be free of charge. Charging is-- allowed only for value added services. Value added services-- would include copying fees, modifications, customizations, and-- inclusion in other product
Update : 2024-12-23 Size : 2kb Publisher : 江浩
dram Downloaded：0: 4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modi
Update : 2024-12-23 Size : 1kb Publisher : 江浩
1032yiwei_new Downloaded：0: CPLD LATTICE1032 test model code
Update : 2024-12-23 Size : 2kb Publisher : 冯达
FIR低通滤波器部分模块 Downloaded：0: This a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Update : 2024-12-23 Size : 5kb Publisher : 吴健宇
数字电子钟 Downloaded：0: digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and
Update : 2024-12-23 Size : 7kb Publisher : 吴健宇
数字锁相环 Downloaded：0: digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate lin
Update : 2024-12-23 Size : 122kb Publisher : 于洪彪
NO_2_ColorLight Downloaded：0: this is the Lantern example VHDL procedures inside covers 48 species of Carnival changes adopted maxplus certification, and the plane through experiments
Update : 2024-12-23 Size : 101kb Publisher : 何蓥
flash接口控制_verilog Downloaded：0: flash interface controller VHDL and Verilog source code and procedures Testbench
Update : 2024-12-23 Size : 850kb Publisher : 李楠

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