VHDL-FPGA-Verilog List Page 4275

VHDL-FPGA-Verilog list

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hdb3 decoder Downloaded：0: I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Update : 2024-12-23 Size : 117kb Publisher : 王薇
Key16 Downloaded：0: 4x4 keyboard module. The documents include ordinary keyboard design program descriptions and procedures related to the original.
Update : 2024-12-23 Size : 49kb Publisher : 波波
inface Downloaded：0: an interface to the control board CPLD logic circuit design process.
Update : 2024-12-23 Size : 4kb Publisher : 欧阳锋
fen Downloaded：0: Verilog, 4,5 dividers, five dividers ratio of 3:2
Update : 2024-12-23 Size : 150kb Publisher : 搞广鹤
pn_code Downloaded：0: coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
Update : 2024-12-23 Size : 35kb Publisher : 高广鹤
fpga加密设计方法 Downloaded：0: FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful
Update : 2024-12-23 Size : 183kb Publisher : 陶伟炯
file_verilog Downloaded：0: the documents on the CPLD, and the C language is close to that of the five counters one.
Update : 2024-12-23 Size : 242kb Publisher : 罗国才
ad cvtor Downloaded：0: development environment : maxplus2 a/d convortor
Update : 2024-12-23 Size : 2kb Publisher : 丁智罡
DISPLAY-vhdl Downloaded：0: VHDL description of the display code development environment maxplus2
Update : 2024-12-23 Size : 1kb Publisher : 丁智罡
ERFREE_COUNTER-vhdl Downloaded：0: maxplus2 VHDL environment for the development of free counter preparation procedures
Update : 2024-12-23 Size : 12kb Publisher : 丁智罡
KEYBOARD_DEC-vhdl Downloaded：0: maxplus2 VHDL development environment for the preparation of the keyboard procedures
Update : 2024-12-23 Size : 1kb Publisher : 丁智罡
SCAN-vhdl Downloaded：0: maxplus2 VHDL development environment for the preparation of a scanning program
Update : 2024-12-23 Size : 1kb Publisher : 丁智罡

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