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VHDL-FPGA-Verilog list
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uart_vhdl_lattice
Downloaded:0
serial port simulated programme of lattice
Update
: 2024-12-23
Size
: 42kb
Publisher
:
赵兴涛
VHDL源代码1
Downloaded:0
VHDL source code
Update
: 2024-12-23
Size
: 4kb
Publisher
:
宋涛
VHDL源代码2
Downloaded:0
and VHDL source code
Update
: 2024-12-23
Size
: 5kb
Publisher
:
宋涛
VHDL源代码3
Downloaded:0
and VHDL source code
Update
: 2024-12-23
Size
: 9kb
Publisher
:
宋涛
VHDL源代码4
Downloaded:0
and VHDL source code
Update
: 2024-12-23
Size
: 4kb
Publisher
:
宋涛
循环冗余校验码
Downloaded:0
Cyclic Redundancy Check (pilot reports)
Update
: 2024-12-23
Size
: 50kb
Publisher
:
振臂
数字频率计(试验报告)
Downloaded:0
Digtal Frequency Test(experiment report) suit Raw recruit reference
Update
: 2024-12-23
Size
: 64kb
Publisher
:
振臂
7状态机设计
Downloaded:0
This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!
Update
: 2024-12-23
Size
: 5.09mb
Publisher
:
振臂
VHDL设计进阶
Downloaded:0
"VHDL design" script, useful for beginners, thank you! !
Update
: 2024-12-23
Size
: 864kb
Publisher
:
振臂
ieee-std-1364
Downloaded:0
done, would not have introduced the document on the bar, IEEE1364 standard (open).
Update
: 2024-12-23
Size
: 1.36mb
Publisher
:
周贤
IP core
Downloaded:0
VHDL core of the design, soft-core design
Update
: 2024-12-23
Size
: 405kb
Publisher
:
周贤
verilog2000
Downloaded:0
verilog2000 update, a former control standards. The inclusion of some new support
Update
: 2024-12-23
Size
: 44kb
Publisher
:
周贤
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.72
.73
.74
.75
.76
4277
.78
.79
.80
.81
.82
...
4311
»
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