VHDL-FPGA-Verilog List Page 628

VHDL-FPGA-Verilog list

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Verilog-Divide-by-45-Counter Downloaded：0: Verilog Divide by 4.5 Counter
Update : 2025-01-27 Size : 10kb Publisher : cmags
1_hello Downloaded：0: fpga' s nios hello program, you can quickly learn how to configure fpga nios nucleus
Update : 2025-01-27 Size : 1kb Publisher : 汪洋
9_timer Downloaded：0: fpga' s nios timer program, you can quickly learn how to configure fpga nios nucleus
Update : 2025-01-27 Size : 2kb Publisher : 汪洋
led_demo Downloaded：0: fpga initialize realize led light water experiments, digital timer, as well as the board of each module initialization
Update : 2025-01-27 Size : 5.18mb Publisher : 汪洋
sclk_switch Downloaded：0: Need some clock switching circuit, such as a circuit supports high-speed mode and low-speed mode, the system works in 125M clock, the system clock work at 3M, you need a dynamic clock in this design in high-speed mode at
Update : 2025-01-27 Size : 177kb Publisher : wangfeng
flow_proc Downloaded：0: Pipeline structure is very complicated in the case of using the logic, through the sub-stack, to a complex logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal and increase t
Update : 2025-01-27 Size : 249kb Publisher : wangfeng
DDS Downloaded：0: Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under another reference clock source role overflow when they complete a cycle, a cycl
Update : 2025-01-27 Size : 905kb Publisher : wangfeng
SP_SCH(Executable) Downloaded：0: The scheduler typically include SP, RR, WFQ, etc., SP scheduling refers to the absolute high-priority scheduling, dispatching without the weight of such concepts, in accordance with the priority scheduling. Four buttons
Update : 2025-01-27 Size : 6.49mb Publisher : wangfeng
SPI Downloaded：0: Based FPGA, SPI bus implementations Verilog language, the top add your own content you want to transfer to the appropriate address on the line, can be hundred percent.
Update : 2025-01-27 Size : 8kb Publisher :
AD9362 Downloaded：0: Based xilinx S6, verilog language, achieve AD9362, design IDDR ODDR interface, has been the actual test
Update : 2025-01-27 Size : 2kb Publisher :
AD80305 Downloaded：0: Based xilinx FPGA S6, verilog realize AD80305 input and output interface configuration, refer to
Update : 2025-01-27 Size : 3kb Publisher :
data_switch Downloaded：0: verilog to achieve mutual conversion between 15bit data with 176bit data can make certain changes based on this code, you can achieve the conversion of other bit-wide data
Update : 2025-01-27 Size : 2kb Publisher :

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