VHDL-FPGA-Verilog List Page 626

VHDL-FPGA-Verilog list

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convertermat Downloaded：0: Embedded applications have emerged appreciably during the past few years due to the considerable increase of nomad and traveller ways of life. These itinerant lifestyles induce the apparition and development of more and
Update : 2025-01-27 Size : 1.8mb Publisher : shankar.m
matlabtoconver Downloaded：0: Embedded applications have emerged appreciably during the past few years due to the considerable increase of nomad and traveller ways of life. These itinerant lifestyles induce the apparition and development of more and
Update : 2025-01-27 Size : 3kb Publisher : shankar.m
matlabtomodelsim Downloaded：0: matlab to model sim converter coding of vhdl code ypu want to convert that matlab into the xilinx platform model sim simulator
Update : 2025-01-27 Size : 1kb Publisher : shankar.m
ldpc-code Downloaded：0: ldpc codes are low dencity paRity checking matrix to check the parity on matrix based g and h algorithm based on algorithm matrix input will be added to this code
Update : 2025-01-27 Size : 9kb Publisher : shankar.m
ldpc-decoder-code Downloaded：0: Specify the decision method used for decoding as one of Hard decision | Soft decision . The default is Hard decision . When you set this property to Hard decision , the output is decoded bits of double or logical data ty
Update : 2025-01-27 Size : 2kb Publisher : shankar.m
UART Downloaded：0: (1) Design UART receiver module receives serial data (RS232 serial communication) the PC to the FPGA (2) Design UART transmit module on FPGA, the hexadecimal value of the data received the PC plus one re-sent to the PC
Update : 2025-01-27 Size : 563kb Publisher : shan
DDS Downloaded：0: Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitude (chips generally obtained through look-up table). Generally digitized sine wave output o
Update : 2025-01-27 Size : 5.67mb Publisher : 网窝囊
mpi Downloaded：0: MPI interface is an interface for communication between the CPU and the logic, the general way of using the bus, the bus generally have two standards, one is MOTO mode, the other one is intel model.
Update : 2025-01-27 Size : 108kb Publisher : 网窝囊
flow_proc Downloaded：0: FPGA FLOW verilog To a complex pipeline logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal, increasing the frequency. The chip area for time, that area in exchange for freq
Update : 2025-01-27 Size : 240kb Publisher : 网窝囊
RR_SCH(Executable) Downloaded：0: FPGA VERILOG The scheduler typically include SP, RR, WRR, WFQ, etc., RR refers to the round robin scheduling, dispatching without the weight of such concepts, even polling scheduling.
Update : 2025-01-27 Size : 3.52mb Publisher : 网窝囊
sclk_switch Downloaded：0: fpga verilog Need some clock switching circuit, such as a circuit supports high-speed mode and low-speed mode, the system works in 125M clock, the system clock work at 3M, you need a dynamic clock in this design in high-
Update : 2025-01-27 Size : 187kb Publisher : 网窝囊
TCAM Downloaded：0: FPGA VERILOG TCAM (ternary content addressable memory) is a ternary content addressable memory, mainly used to quickly find ACL, routing entries.
Update : 2025-01-27 Size : 964kb Publisher : 网窝囊

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