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VHDL-FPGA-Verilog list
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The code function is to realize the dead zone control of the pulse signal. The dead zone of 10us is realized according to the input pulse, and the direct connection of IGBT is avoided.
Update : 2024-12-25 Size : 1kb Publisher : FollowSky

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pipe for help leaner in start stage get more about how to conduct petri net
Update : 2024-12-25 Size : 1.97mb Publisher : tiashiaimeili

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The standard IIC communication protocol has been used in the project. On the basis of IIC, the configuration and detection function of the register can be added.
Update : 2024-12-25 Size : 2kb Publisher : 橙子很好吃

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With the IIC driver, the program can automatically detect whether the hardware's register configuration parameters are correct. The program has been used in the project.
Update : 2024-12-25 Size : 2kb Publisher : 橙子很好吃

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The IIC slave terminal has been used in the project. It can be applied to all kinds of transmission rate, inter board communication and less interfaces. The program can achieve multi parameter transmission and condition
Update : 2024-12-25 Size : 3kb Publisher : 橙子很好吃

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DS18B20 single line temperature sensor drive, can be directly on the board.
Update : 2024-12-25 Size : 23kb Publisher : 橙子很好吃

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The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.
Update : 2024-12-25 Size : 8kb Publisher : 橙子很好吃

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Implementation of camerallink arbitrary bit series conversions
Update : 2024-12-25 Size : 4.43mb Publisher : 非要起名字

ReedSolomon FEC used in RTP
Update : 2024-12-25 Size : 292kb Publisher : HHHHLELE

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Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate
Update : 2024-12-25 Size : 3.11mb Publisher : zhaodameng

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Basys3 4 select a data selector code
Update : 2024-12-25 Size : 18kb Publisher : LEWIS_liu

Gigabit Ethernet related information
Update : 2024-12-25 Size : 2.57mb Publisher : 黑加仑kiskis
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