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Artix7 XC7A100T chip control Gigabit PHY two layer communication, source code
Date : 2025-08-12 Size : 15.51mb User : kang24 -
Two layer communication Artix7 XC7A100T chip control PHY megabytes, source code
Date : 2025-08-12 Size : 15.42mb User : kang24 -
Examine your code to determine if this port should be declared as an INOUT, or if the assignment to this port should not have been made. If this signal connects to submodules, consider the type and lower-level functional
Date : 2025-08-12 Size : 158kb User : 超93 -
The SPI code written in Verilog is readable and writable. After the simulation is finished, it is not yet on board. Awkwardly, it is mainly that official restrictions can not be downloaded from the official limit to ~ ~
Date : 2025-08-12 Size : 1kb User : 你到底是谁 -
The design of a simple electronic organ based on VHDL, with the automatic playing and the use of keystrokes to make different tones
Date : 2025-08-12 Size : 122kb User : 找你呢 -
The USRP system, the FPGA source of the B210 product, is still more valuable.
Date : 2025-08-12 Size : 31.45mb User : ljafjaie -
DE1-SOC experiment development board and Verilog HDL language interactive program works. Our group chooses obstacle avoidance car as curriculum design topic, and according to the selected topic, we have designed the foll
Date : 2025-08-12 Size : 20.17mb User : Sven111 -
In the quartus software, the IP kernel of FFT is called, and the driver module of the IP kernel is edited, so that the IP kernel is read into the data for processing and output data. Use Modelsim for joint simulation.
Date : 2025-08-12 Size : 26.28mb User : XHF72 -
verilog codes for different basic digital circuits elements
Date : 2025-08-12 Size : 38kb User : guy03 -
verilog codes for different basic digital circuits elements new
Date : 2025-08-12 Size : 34kb User : guy03 -
verilog-HDL codes for different basic digital circuits elements
Date : 2025-08-12 Size : 26kb User : guy03 -
HDL code using verilog
Date : 2025-08-12 Size : 19kb User : guy03