VHDL-FPGA-Verilog List Page 64

VHDL-FPGA-Verilog list

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VGA_Display Downloaded：0: The display of the picture is realized by VGA. The code is available and has been verified.
Update : 2024-12-24 Size : 8.16mb Publisher : ayasp
Xilinx开发板初学者问题总结 Downloaded：0: Summary of problems encountered in the development of XILINX series FPGA
Update : 2024-12-24 Size : 747kb Publisher : 鱼在在藻
9516 Downloaded：0: 9516 register configuration, there is a detailed English note, easy to understand, worth a look at
Update : 2024-12-24 Size : 5kb Publisher : 1234李四
方案二 Downloaded：0: This system is a CPLD microcontroller for signal frequency and period, time interval and the duty ratio of digital frequency measurement meter based on the system by the AGC (automatic gain control) circuit, amplifier ci
Update : 2024-12-24 Size : 76kb Publisher : 小竹丶
7f8da115f83d72b263e5818b9374e466 Downloaded：0: PLL configuration using FPGA IN VERILOG LANGUAGE FOR BEGINNER
Update : 2024-12-24 Size : 1.55mb Publisher : nassrou
08167129pllverilog Downloaded：0: PLL CONFIGUARTION USING FOAGA IN VERILOG LANGUAGE
Update : 2024-12-24 Size : 192kb Publisher : nassrou
17416335PLLfpgapaper Downloaded：0: PLL CONFIGURATION USING FPGA IN VERILOG LANGUAGE
Update : 2024-12-24 Size : 280kb Publisher : nassrou
31767694FPGA-PLL Downloaded：0: PLL CONFIGURATION USING FPGA
Update : 2024-12-24 Size : 324kb Publisher : nassrou
37148515LC Downloaded：0: PLL CONFIGUARTION USING FPGA
Update : 2024-12-24 Size : 286kb Publisher : nassrou
aes-master Downloaded：0: aes master by vhdl code and decode
Update : 2024-12-24 Size : 67kb Publisher : Nguyen Nam
aes128-hdl-master Downloaded：0: Verilog AES hdl key 128 bit code and decode
Update : 2024-12-24 Size : 836kb Publisher : Nguyen Nam
aes-project-master Downloaded：0: aes project vhdl FPGA
Update : 2024-12-24 Size : 1.05mb Publisher : Nguyen Nam

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