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counter
Downloaded:0
Code based on FPGA, a realization of VHDL/counter
Update
: 2024-12-24
Size
: 24kb
Publisher
:
yida008
Vivado_2037
Downloaded:0
vivado 2015.4 lisence
Update
: 2024-12-24
Size
: 2kb
Publisher
:
ji100
seg_1
Downloaded:0
Time module, digital tube display, format: time, minute, second
Update
: 2024-12-24
Size
: 5.6mb
Publisher
:
1Q84
oc8051
Downloaded:0
Source code of oc8051
Update
: 2024-12-24
Size
: 651kb
Publisher
:
Abulei
DDS30k
Downloaded:0
Verilog was used to generate sine and triangle wave signals based on direct digital frequency synthesis in quartus development platform.
Update
: 2024-12-24
Size
: 5.93mb
Publisher
:
gmj3841168
try4
Downloaded:0
Using MIF files to generate ROM/RAM with example programs and test files
Update
: 2024-12-24
Size
: 3.11mb
Publisher
:
imdouniwan
SDRAM
Downloaded:0
SDRAM programming code, FPGA design code.
Update
: 2024-12-24
Size
: 9.29mb
Publisher
:
FPGA110
F429编码器例程
Downloaded:0
The accurate output of the encoder is developed using the F429 core plate of the positive atom.
Update
: 2024-12-24
Size
: 10mb
Publisher
:
西海的鱼
BMD_design_gen2_x4_Chipscope
Downloaded:0
This file is Xilinx's PCIE demonstration document that validates the basic functions of the implementation of PCIE
Update
: 2024-12-24
Size
: 8.92mb
Publisher
:
chunjingshui
JTD SJ
Downloaded:0
Using 16 bit MCU, LCD module, small lamp module, timer module, serial communication module. Design a traffic light.
Update
: 2024-12-24
Size
: 415kb
Publisher
:
穆徽月依
Description
Downloaded:0
Altera software examples Cyclone IV
Update
: 2024-12-24
Size
: 2.95mb
Publisher
:
TreyWilliams
KEY2_TEST
Downloaded:0
Altera firmware examples for Cyclone IV
Update
: 2024-12-24
Size
: 2.81mb
Publisher
:
TreyWilliams
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