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VHDL-FPGA-Verilog list
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Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.
Update : 2024-12-24 Size : 46.66mb Publisher : 小天夫斯基

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The implementation of CRC32 is the result of 32bit check of cyclic redundancy check.
Update : 2024-12-24 Size : 1kb Publisher : 大圣啊哈哈

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check the file, its the IETE pics
Update : 2024-12-24 Size : 5.42mb Publisher : usha1234

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Motor speed controller using VHDL
Update : 2024-12-24 Size : 802kb Publisher : Msri

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Digital voltmeter based on FPGA
Update : 2024-12-24 Size : 4kb Publisher : duhai

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command prompt too all
Update : 2024-12-24 Size : 114kb Publisher : boneklawas

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verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.
Update : 2024-12-24 Size : 3kb Publisher : sanh

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a state machine in vhdl
Update : 2024-12-24 Size : 296kb Publisher : Tabbie

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this is a simple arithmetic logic unit in vhdl
Update : 2024-12-24 Size : 476kb Publisher : Tabbie

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a simple counter code in vhdl
Update : 2024-12-24 Size : 1.18mb Publisher : Tabbie

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Design of FPGA taillight
Update : 2024-12-24 Size : 229kb Publisher : Mineoo

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adding 4 bit numbers using vhdl
Update : 2024-12-24 Size : 9kb Publisher : ABHIP
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