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VHDL-FPGA-Verilog list
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The addition of IP core adder to the vivado platform developed by Xilinx is applied.
Update : 2024-12-24 Size : 1.9mb Publisher :

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Using IP core -rom in vivado platform developed by Xilinx, storage is implemented.
Update : 2024-12-24 Size : 50kb Publisher :

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We use the vivado platform developed by Xilinx to realize the down conversion function.
Update : 2024-12-24 Size : 41.16mb Publisher :

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Using the vivado platform developed by Xilinx, the function of calling romIP core is implemented.
Update : 2024-12-24 Size : 4.52mb Publisher :

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Using the vivado platform developed by Xilinx, we can realize the function of calling down the 1bitpwm signal to realize the down conversion.
Update : 2024-12-24 Size : 34.83mb Publisher :

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8-bit ALU Design is an unit of computer, it can process computation and logic.
Update : 2024-12-24 Size : 658kb Publisher : 陳陳

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You should upload 5 codes/documents files2
Update : 2024-12-24 Size : 10kb Publisher : freeskit

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LPDDR2 project, alteral's C5 chip, has been verified on board and can be directly used.
Update : 2024-12-24 Size : 2.2mb Publisher : 橙子很好吃

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FPGA input clock frequency 50Mhz, try to design a frequency divider to realize 1Hz count signal. Requirements: writing design modules; Write the test model.
Update : 2024-12-24 Size : 20.95mb Publisher : pluss

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An adder tree is used to design the 8 bit multiplier, which has a pipelined 7 order FIR filter. The input sequence signal is 4 bits, and it is an unsigned number.
Update : 2024-12-24 Size : 1kb Publisher : mofeizq

Relevant instructions on FPGA Technology
Update : 2024-12-24 Size : 5.67mb Publisher : chuckhang

Introduction to the use of black gold FPGA method, simple to the complex, start slowly
Update : 2024-12-24 Size : 86.46mb Publisher : 意中人8383
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