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VHDL-FPGA-Verilog list
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at7_ex04
Downloaded:0
Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and
Update
: 2024-12-24
Size
: 1.75mb
Publisher
:
24fh
at7_ex05
Downloaded:0
The PC terminal sends data to FPGA through UART. FPGA sends the received data back to the PC end by UART.
Update
: 2024-12-24
Size
: 736kb
Publisher
:
24fh
DLL_clock_generator
Downloaded:0
DLL is useful for the ug and pg sdents tu
Update
: 2024-12-24
Size
: 79kb
Publisher
:
rvm_82
Aircon
Downloaded:0
VHDL code for air con
Update
: 2024-12-24
Size
: 4.05mb
Publisher
:
Tokyosn1
float_multi_module
Downloaded:0
Float_multi_module implements single precision floating point multiplication.
Update
: 2024-12-24
Size
: 1kb
Publisher
:
sisuozheweilai
pwm
Downloaded:0
This program can output PWM waveforms with different duty cycles (0-100) and different frequencies, and meet the needs of different hardware drivers.
Update
: 2024-12-24
Size
: 7.12mb
Publisher
:
DA北岛
C5G_SRAM_RTL_Test
Downloaded:0
The SRAM project of official website C5 board can be used directly
Update
: 2024-12-24
Size
: 476kb
Publisher
:
橙子很好吃
nhan 4 bit
Downloaded:0
example about multiple booth 2 in vhdl
Update
: 2024-12-24
Size
: 228kb
Publisher
:
tahuu
xapp794
Downloaded:0
It is divided into eight experiments, which teach you to use system genertor for DSP step by step to generate IP core files that can be used for vivado.
Update
: 2024-12-24
Size
: 39.76mb
Publisher
:
锤子1998
uart程序
Downloaded:0
the connect of uart
Update
: 2024-12-24
Size
: 11kb
Publisher
:
DTGo
led
Downloaded:0
Verilog control LED lamp based on FPGA development board
Update
: 2024-12-24
Size
: 7kb
Publisher
:
你亲爱的父亲
16QAM
Downloaded:0
It can realize the simulation of random sequence and 16QAM, Verilog language programming, Modelsim and QUARTUS co simulation.
Update
: 2024-12-24
Size
: 5.31mb
Publisher
:
vincent-7
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