VHDL-FPGA-Verilog List Page 56

VHDL-FPGA-Verilog list

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14_ethernet_test Downloaded：0: Xilinx UDP Ethernet communication test has been tested and can be directly used.
Update : 2024-12-24 Size : 6.82mb Publisher : xsbdkxj
pinlvji Downloaded：0: This document is used to measure the frequency of the Verilog code, the source code of a typical digital frequency meter
Update : 2024-12-24 Size : 11kb Publisher : sapphire2
multi_cpu Downloaded：0: The main functions include: According to the 1. / / CPU small system specifications, the realization of the register read and write control functions 2. / / achieve a part of the CPU configuration word read function 3. /
Update : 2024-12-24 Size : 6kb Publisher : fengyuanzyt
uart_55x_lite Downloaded：0: The module is designed and modeled on ST16C554 chip. A) Localbus bus interface; B) multi-channel design. The maximum number of channels is 4, and the number of actual channels is configurable. C) two interrupt modes, sup
Update : 2024-12-24 Size : 35kb Publisher : fengyuanzyt
ad73311 Downloaded：0: AD73311 chip control and data program
Update : 2024-12-24 Size : 5kb Publisher : fengyuanzyt
ambo2000 Downloaded：0: AMBE2000 chip control and coding control, rate control, mature and configurable control module.
Update : 2024-12-24 Size : 8kb Publisher : fengyuanzyt
i2c_slave Downloaded：0: I2C slave module supports multiple I2C modes, which is stable, mature and convenient to use.
Update : 2024-12-24 Size : 8kb Publisher : fengyuanzyt
myclock Downloaded：0: This is a 12-hour digital clock, hout designates the hour, mout designates the minute, sout designates the second, and pout designates morning or afternoon. For example, if current time is 3:08:12 pm, then hout = 3, mout
Update : 2024-12-24 Size : 680kb Publisher : ssttt
DE2_synthesizer Downloaded：0: based on DE2 FPGA 2C35 development board design music synthesizer string base
Update : 2024-12-24 Size : 4kb Publisher : thermon
led_test Downloaded：0: The water lamp routine is the start procedure of FPGA, and initially understands the timing of FPGA.
Update : 2024-12-24 Size : 737kb Publisher : Agnes001
at7_ex01 Downloaded：0: The 8 LED executes the flow light. The flow light is turned on and out in turn. Verilog code based on vivado platform
Update : 2024-12-24 Size : 512kb Publisher : 24fh
at7_ex03 Downloaded：0: Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform
Update : 2024-12-24 Size : 721kb Publisher : 24fh

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