Verilog上机实践参考\Verilog语言练习与讲解.pdf
...................\modelsim使用教程.pdf
...................\HDL编码风格与编码指南.pdf
...................\example_c\example_1.v
...................\.........\example.v
...................\.........\encode8_3_pri.v
...................\.........\encode8_3.v
...................\.........\compare_8b.v
...................\.........\addr_decoder.v
...................\.........\add_4.v
...................\.........\testbench.v
...................\.........\sel_add2.v
...................\.........\sel_add1.v
...................\.........\sel_add.v
...................\.........\mux4_1.v
...................\.........\mult_if_2.v
...................\.........\mult_if_1.v
...................\.........\example_2.txt
...................\.........\LFSR_8bit.v
...................\.........\CNT_LFSR_DIV13.v
...................\.........\LFSR_GENERiC_MOD.v
...................\.........\FSM_1.v
...................\.........\sell_out.v
...................\.........\sell_out_1.v
...................\.........\CNT_LFSR_DIV13_1.v
...................\.........\CNT_LFSR_DIV13_test.v
...................\.........\LFSR_8bit_test.v
...................\.........\sell_out_test.v
...................\.........\CNT_LFSR_DIV13_t.v
...................\.........\one_bit_adder.v
...................\.........\serial_detected.v.bak
...................\.........\serial_detected_test.v
...................\.........\serial_detected.v
...................\.........\fsm_3_modify.v
...................\.........\fsm_test.v
...................\.........\fsm_3.v
...................\.........\fsm_2.txt
...................\.........\transcript
...................\.........\sel.mpf
...................\.........\modelsim.ini
...................\.........\新建 文本文档.txt
...................\.........\tcl_stacktrace.txt
...................\.........\work\_info
...................\.........\work
...................\example_c
Verilog上机实践参考