Description: The code is implemented in fpga a dds, program has three buttons: a control generated waveform (sine or square wave), the other two control the frequency increase or decrease. Program with comments, and success in signaltap the simulation.
- [DDS1-2] - FPGA design using a direct digital synth
- [dds5.0] - DDS power supply design, use of LPM_FILE
- [dds] - dds
- [dds] - Under the DDS in quartus design, Verilog
- [uart] - Debug Assistant is achieved using serial
File list (Check if you may need any files):
DDS\data.mif
...\data.mif.bak
...\datarom.bsf
...\datarom.v
...\datarom_bb.v
...\datarom_wave0.jpg
...\datarom_waveforms.html
...\.b\altsyncram_2k81.tdf
...\..\altsyncram_abq1.tdf
...\..\altsyncram_e4p3.tdf
...\..\altsyncram_g4p3.tdf
...\..\altsyncram_gs61.tdf
...\..\altsyncram_qdq1.tdf
...\..\altsyncram_sdq1.tdf
...\..\altsyncram_u1p3.tdf
...\..\cntr_44j.tdf
...\..\cntr_5bi.tdf
...\..\cntr_8bi.tdf
...\..\cntr_dbi.tdf
...\..\cntr_h1j.tdf
...\..\cntr_t9i.tdf
...\..\cntr_uti.tdf
...\..\dds.asm.qmsg
...\..\dds.asm_labs.ddb
...\..\dds.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.atm
...\..\dds.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.logdb
...\..\dds.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
...\..\dds.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb
...\..\dds.cbx.xml
...\..\dds.cmp.bpm
...\..\dds.cmp.cdb
...\..\dds.cmp.ecobp
...\..\dds.cmp.hdb
...\..\dds.cmp.logdb
...\..\dds.cmp.rdb
...\..\dds.cmp.tdb
...\..\dds.cmp0.ddb
...\..\dds.cmp2.ddb
...\..\dds.cmp_bb.cdb
...\..\dds.cmp_bb.hdb
...\..\dds.cmp_bb.logdb
...\..\dds.cmp_bb.rcf
...\..\dds.dbp
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.eda.qmsg
...\..\dds.fit.qmsg
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.map.bpm
...\..\dds.map.cdb
...\..\dds.map.ecobp
...\..\dds.map.hdb
...\..\dds.map.logdb
...\..\dds.map.qmsg
...\..\dds.map_bb.cdb
...\..\dds.map_bb.hdb
...\..\dds.map_bb.logdb
...\..\dds.merge_hb.atm
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.psp
...\..\dds.pss
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.signalprobe.cdb
...\..\dds.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm
...\..\dds.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.logdb
...\..\dds.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
...\..\dds.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.smp_dump.txt
...\..\dds.syn_hier_info
...\..\dds.tan.qmsg
...\..\dds.tis_db_list.ddb
...\..\decode_aoi.tdf
...\..\decode_rqf.tdf
...\..\logic_util_heursitic.dat
...\..\mux_7oc.tdf
...\..\mux_coc.tdf
...\..\prev_cmp_dds.asm.qmsg
...\..\prev_cmp_dds.eda.qmsg
...\..\prev_cmp_dds.fit.qmsg
...\..\prev_cmp_dds.map.qmsg
...\..\prev_cmp_dds.qmsg
...\..\prev_cmp_dds.tan.qmsg
...\dds.asm.rpt
...\dds.done
...\dds.dpf
...\dds.eda.rpt
...\dds.fit.rpt
...\dds.fit.smsg
...\dds.fit.summary
...\dds.flow.rpt
...\dds.jdi
...\dds.map.rpt
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