mt48lc16m4a2 DDR2 Simulation Model - CodeBus

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VHDL-FPGA-Verilog

Title: mt48lc16m4a2

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
9kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
wubign

Description: DDR2 Simulation Model

Downloaders recently: [More information of uploader wubign]

To Search: DDR2

[DDR2LayoutGuide] - DDR2 Module Master Layout Reference Guid
[s3ask_ddr2] - DDR2-400 sample source code for Xilinx S
[DDR_Eye_Patterns] - DDR1 DDR2 DDR3 Eye Patterns
[ddr2_controller] - DDR2 controller design of the original c
[2048Mb_ddr2] - DDR2 Simulation Model
[user_design] - spartan3a-ddr2 (16bits 333M)

File list (Check if you may need any files):

test.v
test.do
wave.do
mt48lc16m4a2.v

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