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Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
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Size: 121399 |
Author: 杰轩 |
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Description: 介绍了采用单片机进行锁相频率合成的技术
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Size: 127043 |
Author: mcuxyb |
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Description: 锁相环的详细仿真程序
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Size: 7694 |
Author: wiwyhaohao |
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Description: verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
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Size: 383668 |
Author: sakajj |
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Description: 详细介绍数字锁相环的工程
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Size: 122510 |
Author: hyl66313@163.com |
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Description: 这是我编写的计算锁相环分频数的一个工具-This is my calculation prepared by the sub- PLL frequency of a tool
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Size: 868352 |
Author: 孟松 |
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Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
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Size: 124928 |
Author: 于洪彪 |
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Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
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Size: 120832 |
Author: 杰轩 |
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Description: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
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Size: 122880 |
Author: zlin |
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Description: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
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Size: 120832 |
Author: |
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Description: 经典锁相环，MATLAB simulink编写，点开即可运行，对于学习锁相环的同学很有帮助(Classic phase-locked loop, written in MATLAB Simulink, point to run, for students learning phase-locked loop helpful)
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Size: 9216 |
Author: wangjainmindafad
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Description: 可实现labview虚拟锁相，不必通过硬件来实现(for labview lock-in loop)
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Size: 183296 |
Author: yymmff
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Description: Gardner位同步算法与锁相环的联合仿真程序.加入了时偏和频偏，能很好地锁定时偏和频偏，得到最佳采样输出。(Gardner bit synchronization algorithm and phase-locked loop joint simulation program, adding time offset and frequency offset, can well lock the bias and frequency offset, get the best sampling output.)
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Size: 2581504 |
Author: fan_xianbao
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Description: UPS锁相环Matlab/simulink仿真(dpll Matlab/simulink)
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Size: 176128 |
Author: 小线圈
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Description: 光伏逆变锁相环，使用DSP28335，实现频率跟踪，首先采样，然后PI，然后输出(Photovoltaic inverter PLL, using DSP28335, to achieve frequency tracking, first sampling, then PI, and then output)
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Size: 882688 |
Author: 豆豆1233321 |
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Description: 锁相放大器是一种对交变信号进行相敏检波的放大器(The lock-in amplifier is a phase sensitive detection amplifier for alternating signal)
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Size: 30720 |
Author: 在这里L |
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Description: 实现电压快速锁相跟踪，尤其是电压不平衡时的电压跟踪(Realizing fast phase locked tracking of voltage)
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Size: 19456 |
Author: llshuoing |
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Description: 讲述并网逆变器中全软件锁相环的设计与实现，，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）(and implementation of all software phase-locked loop in grid connected inverter is described, that is, detecting the positive and negative component of the fundamental wave under unbalanced grid voltage conditions. Explicitly, a positive decoupling phase locked loop (double DQ - PLL) based on a new sequence detector dual synchronous coordinate system (double DQ - PLL) is proposed, which completely eliminates the traditional synchronous reference frame (SRF - PLL PLL) for detection error.)
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Size: 4512768 |
Author: 醚 |
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Description: 通过STM32程序的编写来形成闭环锁相环，锁住波形的稳定，保持系统的稳定。(Through the preparation of STM32 program to form a closed-loop phase-locked loop, lock waveform stability, maintain the stability of the system)
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Size: 37888 |
Author: wuil- |
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