Description: 用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses Platform: |
Size: 635323 |
Author:张稀楠 |
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Description: 用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses Platform: |
Size: 634880 |
Author:张稀楠 |
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Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用
双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、
与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data）
为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和
满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations. Platform: |
Size: 378880 |
Author:lsg |
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Description: FSK/PSK调制顶层文件
，正弦波模块
，正弦波模块初始化文件
，振幅调整及波形选择模块
，频率显示值地址产生模块
，频率步进键核心模块
，弹跳消除电路-FSK/PSK modulation top-level documents, sine-wave modules, module initialization file sine wave, amplitude adjustment and waveform selection module, the frequency of the displayed value address generator module, the frequency of stepping key core modules, bouncing the elimination of circuit Platform: |
Size: 27648 |
Author:libing |
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Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input. Platform: |
Size: 98304 |
Author:宫逢源 |
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Description: 基于ROM的正弦波发生器的设计
一．实验目的
1. 学习VHDL的综合设计应用
2. 学习基于ROM的正弦波发生器的设计
二．实验内容
设计基于ROM的正弦波发生器，对其编译，仿真。
具体要求：
1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based sine wave generator design
1. Purpose of the experiment
1. VHDL Integrated Design and Application of Learning
2. Learning ROM-based sine wave generator design
2. Experimental content
ROM-based sine wave generator design, its compilation, simulation.
Specific requirements:
1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules
Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB.
3. The 50MHz input clock. Platform: |
Size: 17408 |
Author:爱好 |
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Description: 在本设计中，时钟信号通过分频计产生一个理想的目标时钟频率，控制地址发生器计数，地址发生器的计数结果输出给正弦波数据存数ROM，作为其地址，从该地址取出ROM里的存储好的数据，再通过DA转换，将数字信号转换成模拟信号，最后输出给示波器观察。-In this design, the clock signal generated by frequency meter an ideal target clock frequency, the control address generator counts, count result output address generator to keep the number of sine wave data in ROM, as its address, remove the ROM from the address where good data storage, and then through the DA converter, the digital signal into an analog signal, the final output to the oscilloscope. Platform: |
Size: 2502656 |
Author:刘睿阳 |
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Description: 乐曲硬件演奏电路设计
由顶层文件和数控分频、乐曲简谱码对应的分频预置数查表电路、8位二进制计数器（ROM的地址发生器）组成。演奏乐曲“梁祝”，乐曲可改。已经过硬件下载测试（使用芯片EP1C6Q240 Cyclone系列）-Music by the top hardware performance circuit design file and the NC frequency, music notation code number corresponding to the preset frequency look-up table circuit, 8-bit binary counter (ROM address generator) component. Play music " Butterfly Lovers" , music can be changed. Has been downloaded into the test (using the chip EP1C6Q240 Cyclone Series) Platform: |
Size: 388096 |
Author:叶槟 |
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Description: 其中start是开始信号，上升沿启动控制单元；CLK是工作时钟；CtrlAddr是读取控制字时的地址；CtrlData是读取的控制字；Reading是读信号；EOP是本次AD采样完成信号，只有当AD1和AD2均完成后EOP才为高；EN是允许信号，启动分频器、地址发生器；N是分频系数；Addr1和Addr2分别是AD1和AD2数据存储的起始地址；NUM1和NUM2分别是采样点数。
控制字分别表示分频系数为2，AD1起始地址为1，采样点数5，AD2起始地址为3，采样点数为4。
-Where start is the start signal, the rising edge of start control unit CLK is a working clock CtrlAddr is to read the control word address CtrlData is to read the control word Reading is a reading of the signal EOP is a sampling completion signal of this AD, only When the AD1 and AD2 are completed only after the EOP is high EN is the enable signal to start the divider, the address generator N is the frequency factor Addr1 and Addr2 AD1 and AD2 are the starting address of data storage NUM1 and NUM2 sampling points, respectively. Control word frequency factor, respectively, 2, AD1 starting address is 1, sampling point 5, AD2 start address is 3, the sampling points to 4. Platform: |
Size: 1024 |
Author:谢明 |
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Description: 设计基于ROM的正弦波发生器，对其编译，仿真。
具体要求：
1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。-ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch module 2 waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64 point sine wave data, waveform data obtained using MATLAB. 3 to 50MHz clock as input. Platform: |
Size: 65536 |
Author:坐听晚风赏晚霞 |
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Description: EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。-Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
Platform: |
Size: 33792 |
Author:王丽丽 |
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Description: 随机IPv4地址生成程序，不是很复杂，如果需要批量生成，可自行修改。-Random IPv4 address generator is not very complicated, if you need bulk generation, free to modify. Platform: |
Size: 9099264 |
Author:刘建 |
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Description: 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能，且数据ROM 在高速条件下，占用最少的逻辑资源，设计流程最便捷，波形数据获最方便。下图是此信号发生器结构图，顶层文件SINGT.VHD 在FPGA 中实现，包含2 个部分：ROM 的地址信号发生器，由5 位计数器担任，和正弦数据ROM，拒此，ROM由LPM_ROM模块构成能达到最优设计，LPM_ROM底层是FPGA中的EAB或ESB等。地址发生器的时钟CLK的输入频率f0与每周期的波形数据点数（在此选择64 点），以及D/A输出的频率f 的关系是：f=f0/64。-Sinusoidal signal generator design, the structure of the sinusoidal signal generator consists of three parts. The data counter, or address generator, data ROM and D/A. The good performance of the sinusoidal signal generator design requirements Part 3 high-speed performance, and the ROM data in high-speed conditions, take up minimal logic resources, the design process is the most convenient, the waveform data is the most convenient. The following figure is a block diagram of this signal generator, top file SINGT.VHD is implemented in FPGA, consists of two parts: ROM address signal generator, served by the 5-bit counter, and the sine ROM reject this ROM by LPM_ROM module constitute optimal design LPM_ROM is the underlying FPGA EAB or ESB. The address generator clock CLK input frequency f0 and per period of the waveform data points selected in (64), and the relationship between D/A output frequency f is: f = f0/64. Platform: |
Size: 1825792 |
Author:吴祥 |
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Description: 6 IPv6报文封装及地址生成程序,包含相关代码及说明-6 IPv6 packets are encapsulated and address generation process, including the relevant code and description Platform: |
Size: 163840 |
Author:关红叶 |
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