Search - Alu by verilog

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[Other resource] alu DL : 0: verilog编写的alu模块-Verilog modules prepared by the ALU
Update : 2008-10-13 Size : 1.36kb Publisher : 刘陆陆
[VHDL-FPGA-Verilog] alu DL : 0: verilog编写的alu模块-Verilog modules prepared by the ALU
Update : 2025-02-17 Size : 1kb Publisher : 刘陆陆
[VHDL-FPGA-Verilog] alu_inverter DL : 0: 4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
Update : 2025-02-17 Size : 18kb Publisher : bob
[VHDL-FPGA-Verilog] alu_32_bit DL : 0: verilog 32-bit ALU-verilog 32-bit ALU
Update : 2025-02-17 Size : 2kb Publisher : qwasqwas
[ARM-PowerPC-ColdFire-MIPS] ALU DL : 0: 用verilog编写的4位ALU，由算术运算模块、逻辑运算模块、选择模块组成-Verilog prepared with 4 ALU, arithmetic operations by the module, logic operations module, select modules
Update : 2025-02-17 Size : 3kb Publisher : 姚伟
[VHDL-FPGA-Verilog] alu3 DL : 0: 用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作-Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating
Update : 2025-02-17 Size : 199kb Publisher : 徐芬
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Update : 2025-02-17 Size : 4.72mb Publisher : 石
[VHDL-FPGA-Verilog] alu DL : 0: the 8 bit alu by verilog
Update : 2025-02-17 Size : 89kb Publisher : pedram
[VHDL-FPGA-Verilog] jf DL : 0: verilog编写的alu模块4bit ALU（运算逻辑单元）的设计给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出-Verilog modules prepared by the ALU4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Update : 2025-02-17 Size : 1kb Publisher : 王川
[VHDL-FPGA-Verilog] VeriRISC_CPU_Verilog DL : 0: Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
Update : 2025-02-17 Size : 9kb Publisher : 张昊溢
[VHDL-FPGA-Verilog] alu DL : 0: 32位alu模块实现加减法、逻辑运算、移位、比较和置高位立即数等功能。verilog实现。-32-bit alu module achieves functions like addition and subtraction, logical operations, shift, compare, and set a high immediate number by verilog
Update : 2025-02-17 Size : 886kb Publisher : sherlydunn
[VHDL-FPGA-Verilog] alu DL : 0: verilog 编写的可综合的ALU单元可执行加减与或非 5种运算-verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing
Update : 2025-02-17 Size : 354kb Publisher : peyo
[Other] alu DL : 0: 用Verilog HDL编写的简单算数逻辑单元-Algorithm Logic Unit programmed by Verilog HDl
Update : 2025-02-17 Size : 43kb Publisher : 张娜
[ARM-PowerPC-ColdFire-MIPS] CPU DL : 0: 用Verilog实现的哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成-Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.
Update : 2025-02-17 Size : 4kb Publisher : qiaozhitong
[VHDL-FPGA-Verilog] ALU DL : 0: 用verilog寫成的ALU，有簡易的加減乘除、shifting、logic gate等功能。-Written by verilog ALU, there is a simple addition, subtraction, shifting, logic gate functions.
Update : 2025-02-17 Size : 236kb Publisher : Liu Ching An
[VHDL-FPGA-Verilog] ALU32 DL : 0: 采用booth算法，实现了32位的ALU。(The 32 bit ALU is realized by using the Booth algorithm.)
Update : 2025-02-17 Size : 1.68mb Publisher : jetyeah