Search - Digital clock

[CSharp] Digital Clock

Description: 电子时钟显示程序,小试牛刀-electronic clock display program, test their abilities
Platform: | Size: 11264 | Author: 黄凤仙 | Hits:

[assembly language] 数字时钟CLOCK

Description: 一个数字时钟的汇编语言程序-a digital clock Assembly Language Program
Platform: | Size: 3072 | Author: 野牛 | Hits:

Description: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
Platform: | Size: 2048 | Author: 吴俊泉 | Hits:

[SCM] CLOCK

Description: 51单片机实现数字时钟的程序，输出小时，分，秒显示在数码管上，并可按键调节。-51 single-chip digital clock procedures, output hours, minutes and seconds displayed on the digital tube, and adjust keys.
Platform: | Size: 2048 | Author: zhangbo | Hits:

[assembly language] clock

Description: 基于单片机设计的数字钟的设计，该数字钟功能教齐全有整点报，８路闹钟设置，年月日显示，秒表记时功能．-Single-chip design based on the design of the digital clock, the digital clock function, a whole range teaching points, 8 alarm settings, date display, stopwatch timer functions.
Platform: | Size: 2324480 | Author: 张坤 | Hits:

[SCM] clock

Description: 基于51单片机实现的数字钟用keil编译，并用protues仿真实现。-Based on 51 single-chip realization of digital clock using keil compiler, and realize protues simulation.
Platform: | Size: 53248 | Author: digua | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的VHDL源程序，可实现整点报时、闹钟的功能，还有常有星期的显示，已调试过-Digital Clock in VHDL source code, enabling the whole point timekeeping, alarm clock function, there are often weeks of shows that have been debug
Platform: | Size: 1339392 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] CLOCK

Description: 可以调整时间和设置闹钟的数字钟(VHDL)-Can adjust the time and set the digital clock alarm clock (VHDL)
Platform: | Size: 906240 | Author: iyoung | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[SCM] clock

Description: 多功能电子数字钟的设计带语音报时功能比赛做的 -Multifunction Electronic Digital Clock Design Competition with voice timekeeping function to do the
Platform: | Size: 90112 | Author: philip.chen | Hits:

[SCM] clock

Description: 资料中包括了利用凌阳61板和液晶块搭建一个多功能数字电子钟的源码和完整的电路原理图，理论上只要按照指示做，把程序烧进去，就能马上运行。是我一个完整的毕业设计。-Information, including the use of Sunplus 61 boards and blocks to build a multi-function LCD digital clock source and a complete circuit schematic diagram, in theory, as long as in accordance with the instructions, so that burned into the procedure can be run immediately. I graduated from a complete design.
Platform: | Size: 184320 | Author: 曾明 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
Platform: | Size: 3072 | Author: 幸福 | Hits:

[SCM] digital.clock.with.alarm

Description: 一个用8051单片机开发的程序，是带闹钟的数字时钟，含有原理图-8051 with the development of a procedure for the digital clock with alarm, containing schematic
Platform: | Size: 79872 | Author: 李强 | Hits:

[Embeded-SCM Develop] vhdl-digital-clock-design

Description: 设计一个具有特定功能的数字电子钟。准确计时，以数字形式显示h、min、s 的时间。小时的计时要求为二十四进位，分和秒的计时要求为六十进位。该电子钟上电或按键复位后能自动显示系统提示00-00-00，进入时钟准备状态；第一次按电子钟功能键，电子钟从0时0分0秒开始运行，进入时钟运行状态；再次按电子钟功能键，则电子钟进入时钟调整状态，此时可利用各调整键调整时间，调整结束后可按功能键再次进入时钟运行状态。 -Designed with a specific function of a digital electronic clock. Accurate timing to the digital form h, min, s time. Hours of time requested for the 24 binary, minutes, and seconds of time requested for the 60 binary. The electronic bell power or reset button can automatically display 00-00-00 prompted, enter the clock readiness the first time by e-bell function keys, the electronic bell from 00:00:00 to start running, enter the clock running again by e-bell function keys, the electronic bell to enter the clock adjustment status, at this time can use the adjustment button to adjust the time to adjust after the end of function keys can be re-entering the clock running.
Platform: | Size: 6144 | Author: andy | Hits:

[VHDL-FPGA-Verilog] clock

Description: 本实验实现一个能显示小时，分钟，秒的数字时钟（贝一特电子）Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
Platform: | Size: 1024 | Author: 黄建 | Hits:

[assembly language] complex-digital-clock

Description: 一个多功能数字钟汇编程序，具有基本时钟功能，年月日，秒表，24小时的倒计时，闹钟五个功能。-A multi-functional digital clock assembler with the basic clock function, date, stopwatch, 24-hour countdown, the five functional alarm clock.
Platform: | Size: 2048 | Author: wei | Hits:

[VHDL-FPGA-Verilog] clock

Description: 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.
Platform: | Size: 1041408 | Author: ryan | Hits:

[SCM] LED.clock

Description: 个人做的基于AVR单片机的一个简易数字钟，用C语言写的，希望各位多多指教。-Individual to do a simple microcontroller-based AVR digital clock, using C language to write, and hope that the exhibitions.
Platform: | Size: 3072 | Author: miwuya | Hits:

[VHDL-FPGA-Verilog] digital-clock-design

Description: VHDL语言编写的数字时钟设计程序，含源代码和波形仿真，还有顶层电路设计。-The VHDL language of the digital clock design procedures, including source code and the waveform simulation, but also the circuit design.
Platform: | Size: 13312 | Author: h | Hits:

[VHDL-FPGA-Verilog] Multifunction-digital-clock

Description: 这是多功能数字钟的Verilog源程序，此程序已经编译通过，可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use
Platform: | Size: 493568 | Author: 莫然 | Hits:

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[CSharp] Digital Clock

[assembly language] 数字时钟CLOCK

[MPI] clock

[SCM] CLOCK

[assembly language] clock

[SCM] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] CLOCK

[VHDL-FPGA-Verilog] clock

[SCM] clock

[SCM] clock

[VHDL-FPGA-Verilog] clock

[SCM] digital.clock.with.alarm

[Embeded-SCM Develop] vhdl-digital-clock-design

[VHDL-FPGA-Verilog] clock

[assembly language] complex-digital-clock

[VHDL-FPGA-Verilog] clock

[SCM] LED.clock

[VHDL-FPGA-Verilog] digital-clock-design

[VHDL-FPGA-Verilog] Multifunction-digital-clock

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